淡江大學機構典藏:作者相關文件
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    "Yu-Lung Lo"的相關文件 

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    類別 日期 題名 作者 檔案
    [電機工程學系暨研究所] 會議論文 2013-04-08 A GHz Full-Division-Range Programmable Divider with Output Duty-Cycle Improved Yu-Lung Lo; Jhih-Wei Tsai; Han-Ying Liu; Yang, Wei-Bin
    [電機工程學系暨研究所] 期刊論文 2020-03-06 A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications Wei-Bin Yang; Hsi-Hua Wang; Hsin-I Chang; Yu-Lung Lo
    [電機工程學系暨研究所] 期刊論文 2019-02-22 A Fast Transient Response and High Current Efficiency Output-Capacitorless Low Dropout Regulator for Low-Power SoC Applications Wei-Bin Yang; Yu-Hsin Li; Cheng-Yang Yu; Yu-Lung Lo
    [電機工程學系暨研究所] 期刊論文 2018-01 A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4 Yu-Lung Lo; Wei-Bin Yang; Han-Hsien Wang; Cing-Huan Chen; Zi-Ang Huang
    [電機工程學系暨研究所] 期刊論文 2018-01 Wide‑range CMOS reference clock generator with a dynamic duty cycle scaling mechanism at a 0.9‑V supply voltage Wei-Bin Yang; Yu-Lung Lo; Kuo-Ning Chang; Yu-Yao Lin
    [電機工程學系暨研究所] 期刊論文 2017-08-30 Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input Wei‑Bin Yang; Yu-Yao Lin; Yu-Lung Lo
    [電機工程學系暨研究所] 期刊論文 2017-01-30 All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application Chih-Wei Tsai; Yu-Lung Lo; Chia-Chen Chang; Han-Ying Liu; Wei-Bin Yang; Kuo-Hsing Cheng
    [電機工程學系暨研究所] 期刊論文 2016-05-25 A High-Resolution All-Digital Temperature Sensor with Process Variation Compensation Yu-Lung Lo; Wei-Tsuen Chen; Yu-Ting Chiu; Wei-Bin Yang

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