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    Items for Author "Wu, Po-han"  

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    Showing 21 items.

    Collection Date Title Authors Bitstream
    [機械與機電工程學系暨研究所] 學位論文 2016 史蒂芬生第三型六連桿機構運動產生之特例探討 吳柏翰; Wu, Po-Han
    [電機工程學系暨研究所] 學位論文 2013 Power-aware multi-chains encoding scheme for low-cost environment 吳柏翰; Wu, Po-Han
    [電機工程學系暨研究所] 學位論文 2006 A novel hardware architecture for low power and rapid testing of VLSI circuits 吳柏翰; Wu, Po-han
    [電機工程學系暨研究所] 會議論文 2011-09 Multiple Inputs Selector for High-Speed Masking Chen, K-H.; Huang, J-T.; Wu, P-H.; Rau, J-C.
    [電機工程學系暨研究所] 會議論文 2010-10-31 The AB-Filling Methodology for Power-aware At-Speed Scan Testing Chen, Tsung-tang; Wu, Po-han; Chen, Kung-han; Rau, Jiann-chyi; Tzeng, Shih-ming
    [電機工程學系暨研究所] 會議論文 2010-05-30 Multi-Chains Encoding Scheme in Low-Cost ATE 饒建奇; Rau, Jiann-Chyi; Chen, Gong-Han; Wu, Po-Han
    [電機工程學系暨研究所] 會議論文 2010-05-30 Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment 饒建奇; Rau, Jiann-Chyi; Lin, Chu-Chuan; Wu, Po-Han; Chen, Gong-Han
    [電機工程學系暨研究所] 會議論文 2009-11-23 A New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology Chen, Tsung-tang; Li, Wei-lin; Wu, Po-han; Rau, Jiann-chyi
    [電機工程學系暨研究所] 會議論文 2009-11 Low Power Multi-Chains Encoding Scheme for SoC in Low-Cost Environment Wu, Po-han; Rau, Jiann-chyi
    [電機工程學系暨研究所] 會議論文 2009-05-24 Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression Li, Wei-Lin; Wu, Po-Han; Rau, Jiann-Chyi
    [電機工程學系暨研究所] 會議論文 2006-12-04 Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs Rau, Jiann-Chyi; Chen, Chien-Shiun; Wu, Po-Han; 饒建奇; 陳建勳; 吳柏翰
    [電機工程學系暨研究所] 會議論文 2005-05-23 A novel reseeding mechanism for pseudo-random testing of VLSI circuits Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han
    [電機工程學系暨研究所] 期刊論文 2012-06-01 Test Slice Difference Technique for Low-Transition Test Data Compression Rau, Jiann-Chyi; Wu, Po-Han; Li, Wei-Lin
    [電機工程學系暨研究所] 期刊論文 2011-06 Power-aware compression scheme for multiple scan-chain Rau, Jiann-Chyi; Wu, Po-Han; Rau, Jiann-Chyi
    [電機工程學系暨研究所] 期刊論文 2011-03-01 An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han; Rau, Jiann-Chyi
    [電機工程學系暨研究所] 期刊論文 2011-01 Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment Rau, Jiann-Chyi; Wu, Po-Han; Rau, Jiann-Chyi
    [電機工程學系暨研究所] 期刊論文 2010-09-01 Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun; Rau, Jiann-Chyi
    [電機工程學系暨研究所] 期刊論文 2009-01 The Star-Routing Algorithm Based on Manhattan-Diagonal Model for Three Layers Channel Routing Rau, Jiann-chyi; Wu, Po-han; Liu, Chia-jung; Lin, Yi-chen
    [電機工程學系暨研究所] 期刊論文 2008-11 The Efficient TAM Design for Core-Based SOCs Testing Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu
    [電機工程學系暨研究所] 期刊論文 2008-06 A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu; Rau, Jiann-chyi
    [電機工程學系暨研究所] 期刊論文 2008-06 An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing; Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing

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