淡江大學機構典藏:作者相关文件

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"Wei-Bin Yang"的相关文件

类别	日期	题名	作者
[電機工程學系暨研究所] 專利	2008-09-01	時脈產生器以及相關之鎖相迴路與時脈產生方法	郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing
[電機工程學系暨研究所] 專利	2007-09-11	儲存單元以及相關暫存器檔案與處理單元	楊維斌
[電機工程學系暨研究所] 專利	2005-09-23	Programmable fractional-N clock generators	郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing
[電機工程學系暨研究所] 會議論文	2017-05-13	A Multi-Rate QPSK Transmitter for Wearable or Implantable Biomedical Devices	Yang, Pei-Ting; Shih, Horng-Yuan; Yang, Cheng-Wei; Shih, Jung-Tai; Chang, Yu-Chuan; Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2017-05-13	A 12-bit 600MS/s CT ΣΔ ADC for Ultrasound System Applications	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2016-05-28	Wide Range CMOS Reference Clock Generator with Dynamic Duty Cycle Scaling Mechanism in 0.9V Supply Voltage	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2016-05-28	A fast-lock and low-power Delay-Locked-Loop applied for DDR4	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2016-05-28	A Current-Controlled Oscillator with Temperature, Voltage and Process	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2015-05-22	A Transient Enhanced LDO with Current Buffer for SoC Application	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2015-01-28	A new multiple frequency out of DLL with Glitch Elimination and Phase Interpolator	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2014-10-30	A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2014-04-26	Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2014-04-26	A Low Phase Noise All-Digital Programmable DLL-Based Clock Generator	Lo, Yu-Lung; Liu, Han-Ying; Chou, Pei-Yuan; Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2013-11-05	A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration	Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文	2011-06-20	The High-Performance and Low-Power CMOS Output Driver Design	Yang, Wei-bin; Liao, Pei-hsuan; Wang, Chi-hsiung; Cheng, Ching-tsan
[電機工程學系暨研究所] 會議論文	2009-12	A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Shen, Jsung-mo; Yang, Wei-bin; Hsieh, Chang-yu; Lo, Yu-lung
[電機工程學系暨研究所] 會議論文	2009-12	A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller	Gao, Wan-lun; Yang, Wei-bin; Lo, Yu-lung
[電機工程學系暨研究所] 會議論文	2009-09	Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique	Chao, Ting-sheng; Lo, Yu-lung; Yang, Wei-bin; Cheng, Kuo-hsing
[電機工程學系暨研究所] 會議論文	2009-08	A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator	Shen, Jsung-mo; Yang, Wei-bin; Hsieh, Chang-yu; Lo, Yu-lung
[電機工程學系暨研究所] 會議論文	2008-11	A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage	Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin
[電機工程學系暨研究所] 會議論文	2008-04-16	A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III	Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way
[電機工程學系暨研究所] 會議論文	2007-04	A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery	Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin
[電機工程學系暨研究所] 會議論文	2006-12	Analysis and Design of High Performance, Low Power Multiple Ports	Jau, Ting-sheng; Yang, Wei-bin; Chang, Chung-yu
[電機工程學系暨研究所] 會議論文	2006-12	A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler	Jau, Ting-sheng; Yang, Wei-bin; Lo, Yu-lung
[電機工程學系暨研究所] 會議論文	2006-05	The new improved pseudo fractional-N clock generator with 50% duty cycle	Kuo, Shu-chang; Hung, Tzu-chien; Yang, Wei-bin
[電機工程學系暨研究所] 會議論文	2005-08-29	The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle	Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing
[電機工程學系暨研究所] 會議論文	2004-05	A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop	Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming
[電機工程學系暨研究所] 會議論文	2001-09	A difference detector PFD for low jitter PLL	鄭國興; Cheng, Kuo-hsing; Yao, Tse-hua; Jiang, Shu-yu; Yang, Wei-bin
[電機工程學系暨研究所] 會議論文	1997-11-29	Low-voltage-swing low-power CMOS buffer	鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin
[電機工程學系暨研究所] 會議論文	1997-08-21	A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process	鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Laiw, Yii-yih
[電機工程學系暨研究所] 期刊論文	2020-03-06	A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications	Yang, Wei-Bin; Wang, Hsi-Hua; Chang, Hsin-I; Lo, Yu-Lung
[電機工程學系暨研究所] 期刊論文	2018-01	A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4	Yu-Lung Lo; Wei-Bin Yang; Han-Hsien Wang; Cing-Huan Chen; Zi-Ang Huang
[電機工程學系暨研究所] 期刊論文	2017-01-30	All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application	Chih-Wei Tsai; Yu-Lung Lo; Chia-Chen Chang; Han-Ying Liu; Wei-Bin Yang; Kuo-Hsing Cheng
[電機工程學系暨研究所] 期刊論文	2010-09-01	High Efficiency Concurrent Embedded Block Coding Architecture for JPEG 2000	Lin, Tsung-Da; Yang, Wei-Bin; Hsieh, Chang-Yu; Hsieh, Chang-Yu
[電機工程學系暨研究所] 期刊論文	2010-03	A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output	Yang, Wei-Bin; Lo, Yu-Lung; Chao, Ting-Sheng; Yang, Wei-Bin
[電機工程學系暨研究所] 期刊論文	2009-06	High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer	Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing; Lo, Yu-lung
[電機工程學系暨研究所] 期刊論文	2004-10	低功率多輸出入埠暫存器檔案之分析與設計	楊維斌
[電機工程學系暨研究所] 期刊論文	2004-10	動態調整電源電壓與操作頻率以降低系統晶片之功率消耗	楊維斌
[電機工程學系暨研究所] 期刊論文	2003-11	A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop	Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming
[電機工程學系暨研究所] 期刊論文	1999-03	The charge-transfer feedback-controlled split-path CMOS buffer	Cheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi
[電機工程學系暨研究所] 研究報告	2013-08	新型超低輸入電壓與高電流效率之全數位式低壓降線性穩壓電路研製	楊維斌
[電機工程學系暨研究所] 研究報告	2011-08	具高可靠度之低電源電壓參考時脈研製	楊維斌
[電機工程學系暨研究所] 研究報告	2010	具高製程、電壓與溫度容忍度之低功耗參考時脈產生器電路研製	楊維斌
[電機工程學系暨研究所] 研究報告	2009	具資料維持之低靜態功耗暫存器檔案	楊維斌

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