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Items for Author "Lo, Yu-lung"
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Showing 18 items.
Collection
Date
Title
Authors
Bitstream
[電機工程學系暨研究所] 會議論文
2023-09-05
High-Efficiency and Wide-Load Current Range LDO Regulator with Dynamic Loop Gain Control Technique
Chiu, Yu-Chun
;
Lo, Yu-Lung
;
Lin, Chia-Wen
;
Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文
2015-11-09
Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in UMC 0.18um CMOS Process
Yang, Wei-Bin
;
Lin, Yu-Yao
;
Wang, Chi-Hsiung
;
Chang, Kuo-Ning
;
Chen, Cing-Huan
;
Lo, Yu-Lung
[電機工程學系暨研究所] 會議論文
2014-04-26
Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process
Yang, Wei-Bin
;
Lin, Yu-Yao
;
Lo, Yu-Lung
[電機工程學系暨研究所] 會議論文
2014-04-26
A Low Phase Noise All-Digital Programmable DLL-Based Clock Generator
Lo, Yu-Lung
;
Liu, Han-Ying
;
Chou, Pei-Yuan
;
Yang, Wei-Bin
[電機工程學系暨研究所] 會議論文
2011-12-14
Temperature Insensitive Current Reference for the 6.27 MHz Oscillator
Yang, Wei-bin
;
Huang, Zheng-yi
;
Cheng, Ching-tsan
;
Lo, Yu-lung
[電機工程學系暨研究所] 會議論文
2011-12-13
Supply Voltage and Temperature Insensitive Current Reference for the 4 MHz Oscillator
Wang, Chi-hsiung
;
Lin, Cheng-feng
;
Yang, Wei-bin
;
Lo, Yu-lung
[電機工程學系暨研究所] 會議論文
2010-11-21
A New Dynamic Fast-Settling Low Dropout Regulator with Programmable Output Voltage
Yang, Wei-bin
;
Shen, Jsung-mo
;
Chang, Hsiang-hsiung
;
Lo, Yu-lung
[電機工程學系暨研究所] 會議論文
2009-12
A Low Power Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
Shen, Jsung-mo
;
Yang, Wei-bin
;
Hsieh, Chang-yu
;
Lo, Yu-lung
[電機工程學系暨研究所] 會議論文
2009-12
A Pseudo Fractional-N and Multiplier Clock Generator with 50% Duty Cycle Output Using Low Power Phase Combination Controller
Gao, Wan-lun
;
Yang, Wei-bin
;
Lo, Yu-lung
[電機工程學系暨研究所] 會議論文
2009-09
Designing Ultra-Low Voltage PLL Using a Bulk-Driven Technique
Chao, Ting-sheng
;
Lo, Yu-lung
;
Yang, Wei-bin
;
Cheng, Kuo-hsing
[電機工程學系暨研究所] 會議論文
2009-08
A Multi-Voltage Control Technique with Fast-Settling Mechanism for Low Dropout Regulator
Shen, Jsung-mo
;
Yang, Wei-bin
;
Hsieh, Chang-yu
;
Lo, Yu-lung
[電機工程學系暨研究所] 會議論文
2008-04-16
A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III
Cheng, Kuo-hsing
;
Hung, Cheng-liang
;
Chang, Chih-hsien
;
Lo, Yu-lung
;
Yang, Wei-bin
;
Miaw, Jiunn-way
[電機工程學系暨研究所] 會議論文
2006-12
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler
Jau, Ting-sheng
;
Yang, Wei-bin
;
Lo, Yu-lung
[電機工程學系暨研究所] 期刊論文
2018
A current-controlled oscillator with temperature, voltage, and process compensation
Yang, Wei-Bin
;
Chiang, Jen-Shiun
;
Cheng, Ching-Tsan
;
Wang, Chi-Hsiung
;
Shih, Horng-Yuan
;
Syu, Jia-Liang
;
Chen, Cing-Huan
;
Lo, Yu-Lung
[電機工程學系暨研究所] 期刊論文
2011
The High-Performance and Low-Power CMOS Output Driver Design
Cheng, Ching-tsan
;
Wang, Chi-hsiung
;
Liao, Pei-hsuan
;
Yang, Wei-bin
;
Lo, Yu-lung
;
Cheng, Ching-tsan
;
Wang, Chi-hsiung
;
Liao, Pei-hsuan
;
Yang, Wei-bin
;
Lo, Yu-lung
[電機工程學系暨研究所] 期刊論文
2010-03
A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output
Yang, Wei-Bin
;
Lo, Yu-Lung
;
Chao, Ting-Sheng
;
Yang, Wei-Bin
[電機工程學系暨研究所] 期刊論文
2009-06
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer
Lo, Yu-lung
;
Yang, Wei-bin
;
Chao, Ting-sheng
;
Cheng, Kuo-hsing
;
Lo, Yu-lung
[電機工程學系暨研究所] 期刊論文
2009-05-01
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique
Lo, Yu-lung
;
Yang, Wei-bin
;
Chao, Ting-sheng
;
Cheng, Kuo-hsing
;
Lo, Yu-lung
;
Yang, Wei-bin
;
Chao, Ting-sheng
;
Cheng, Kuo-hsing
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