| [電機工程學系暨研究所] 專利 |
2008-09-01 |
時脈產生器以及相關之鎖相迴路與時脈產生方法 |
郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
|
| [電機工程學系暨研究所] 專利 |
2005-09-23 |
Programmable fractional-N clock generators |
郭書菖; Kuo, Shu-chang; 楊維斌; Yang, Wei-bin; 鄭國興; Cheng, Kuo-Hsing |
|
| [電機工程學系暨研究所] 專利 |
1995-01-03 |
CMOS Dynamic Logic Structure |
吳重雨; 鄭國興; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 專利 |
1994-07-11 |
互補式金氧半電晶體(CMOS)動態邏輯架構 |
吳重雨; 鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
2008-04-16 |
A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III |
Cheng, Kuo-hsing; Hung, Cheng-liang; Chang, Chih-hsien; Lo, Yu-lung; Yang, Wei-bin; Miaw, Jiunn-way |
|
| [電機工程學系暨研究所] 會議論文 |
2007-04 |
A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery |
Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin |
|
| [電機工程學系暨研究所] 會議論文 |
2005-08-29 |
The New Approach of Programmable Pseudo Fractional-N Clock Generator for GHz Operation with 50% Duty Cycle |
Yang, Wei-bin; Kuo, Shu-chang; Chu, Yuan-hua; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 會議論文 |
2004-05 |
A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop |
Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
|
| [電機工程學系暨研究所] 會議論文 |
2003-08 |
A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming |
Cheng, Kuo-Hsing; Li, Po-Yu; Chen, Tsung-Shen |
 |
| [電機工程學系暨研究所] 會議論文 |
2003-08 |
Design of Low-Power Content Addressable Memory Cell |
Cheng, Kuo-Hsing; Wei, Chia-Hung; Wu, Chen-Lung |
|
| [電機工程學系暨研究所] 會議論文 |
2003-05-25 |
A new robust handshake for asymmetric asynchronous micro-pipelines |
Cheng, Kuo-hsing; 李揚漢; Lee, Yang-han; Chang, Wei-chun |
  |
| [電機工程學系暨研究所] 會議論文 |
2002-08 |
MOS Charge Pump for Sub-2.0V Operation |
Cheng, Kuo-Hsing; Chang, Chung-Yu |
|
| [電機工程學系暨研究所] 會議論文 |
2002-08 |
Low-Voltage GHz Dynamic Logic Circuit Design |
Cheng, Kuo-Hsing; Lee, Wen-Shiuan |
|
| [電機工程學系暨研究所] 會議論文 |
2002-01-07 |
Prioritized prime implicant patterns puzzle for novel logic synthesis and optimization |
Cheng, Kuo-hsing; Cheng, Shun-wen |
|
| [電機工程學系暨研究所] 會議論文 |
2001-09 |
A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency |
鄭國興; Cheng, Kuo-hsing; Chen, Yu-jung |
|
| [電機工程學系暨研究所] 會議論文 |
2001-09 |
A CMOS low power voltage controlled oscillator with split-path controller |
鄭國興; Cheng, Kuo-hsing; Tzou, Lin-jiunn; Yang, Wen-bin; Sheu, Shyh-shyuan |
|
| [電機工程學系暨研究所] 會議論文 |
2001-09 |
A difference detector PFD for low jitter PLL |
鄭國興; Cheng, Kuo-hsing; Yao, Tse-hua; Jiang, Shu-yu; Yang, Wei-bin |
|
| [電機工程學系暨研究所] 會議論文 |
2001-09 |
Accurate current mirror with high output impedance |
鄭國興; Cheng, Kuo-hsing; Chen, Chi-che; Chung, Chun-fu |
|
| [電機工程學系暨研究所] 會議論文 |
2001-09 |
A 1.2 V 500 MHz 32-bit carry-lookahead adder |
鄭國興; Cheng, Kuo-hsing; Lee, Wen-shiuan; Huang, Yung-chong |
|
| [電機工程學系暨研究所] 會議論文 |
2001-09 |
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning |
鄭國興; Cheng, Kuo-hsing; Cheng, Shun-wen |
|
| [電機工程學系暨研究所] 會議論文 |
2001-05-06 |
A new logic synthesis and optimization procedure |
鄭國興; Cheng, Kuo-hsing; Hsieh, Ven-chieh |
|
| [電機工程學系暨研究所] 會議論文 |
2001-05-06 |
A low-power high driving ability voltage control oscillator used in PLL |
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Chung, Chun-fu |
|
| [電機工程學系暨研究所] 會議論文 |
2001-05 |
ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning |
Cheng, Shun-wen; Cheng, Kuo-hsing; 鄭舜文; 鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
2000-05 |
The Design and implementation of DCT/IDCT Chip with Novel Architecture |
鄭國興; Cheng, Kuo-hsing; Huang, Chih-sheng; Lin, Chun-pin |
|
| [電機工程學系暨研究所] 會議論文 |
2000 |
The non-full voltage swing TSPC (NSTSPC) logic design |
Cheng, Kuo-hsing; Huang, Yung-chong; 鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
2000 |
A low-jitter and low-power phase-locked loop design |
鄭國興; Cheng, Kuo-hsing; Liao, Huan-sen; Tzou, Lin-jiunn |
|
| [電機工程學系暨研究所] 會議論文 |
1999-09-05 |
The novel efficient design of XOR/XNOR function for adder applications |
Cheng, Kuo-hsing; Huang, Chih-sheng; 鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
1999-09-05 |
The suggestion for CFS CMOS buffer |
Cheng, Kuo-hsing; Yang, Wei-bin; 鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
1999-08 |
A Low-Power CMOS Output Buffer |
Cheng, Kuo-Hsing; Yang, Wei-Bin |
|
| [電機工程學系暨研究所] 會議論文 |
1999-05 |
A programmagle delay element for low power PLL applications |
鄭國興; Cheng, Kuo-hsing; Liao, Huan-sen |
|
| [電機工程學系暨研究所] 會議論文 |
1999 |
High efficient 3-input XOR for low-voltage low-power high-speed applications |
Cheng, Kuo-hsing; Hsieh, Ven-chieh; 鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
1998-10-21 |
The design and analysis of pass-transistor logic for low power applicaations |
鄭國興; Cheng, Kuo-hsing; Huang, Tsong-liang; Huang, Chih-sheng |
|
| [電機工程學系暨研究所] 會議論文 |
1998-09-14 |
Low-power all digital down connverter for IS-95 forward link demodulation |
鄭國興; Cheng, Kuo-hsing; Chen, Yu-hsiang |
|
| [電機工程學系暨研究所] 會議論文 |
1998-09-14 |
A linear current controlled delay element for low power applications |
鄭國興; Cheng, Kuo-hsing; Liao, Huan-sen |
|
| [電機工程學系暨研究所] 會議論文 |
1998-09-14 |
An efficient FIR filter design for VLSI implementation |
鄭國興; Cheng, Kuo-hsing; Sun, Cheng-chung |
|
| [電機工程學系暨研究所] 會議論文 |
1998-09-13 |
The Improvement of Conditional Sum Adder for Low Power Applications |
鄭國興; Cheng, Kuo-hsing; Chiang, Shu-min; Cheng, Shun-wen |
|
| [電機工程學系暨研究所] 會議論文 |
1998 |
Low voltage low power high-speed BiCMOS multiplier |
鄭國興; Cheng, Kuo-hsing; Yeha, Yu-kwang; Lian, Farn-sou |
|
| [電機工程學系暨研究所] 會議論文 |
1997-12-15 |
A 1.2 V low-power TSPC complementary pass transistor logic |
鄭國興; Cheng, Kuo-hsing; Chen, Jian-hung |
|
| [電機工程學系暨研究所] 會議論文 |
1997-11-29 |
1.2V low-power dynamic complementary-pass-transistor logic |
鄭國興; Cheng, Kuo-hsing; Chen, Jian-hung |
|
| [電機工程學系暨研究所] 會議論文 |
1997-11-29 |
Low-voltage-swing low-power CMOS buffer |
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin |
|
| [電機工程學系暨研究所] 會議論文 |
1997-08-21 |
A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process |
鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Laiw, Yii-yih |
|
| [電機工程學系暨研究所] 會議論文 |
1997-08 |
A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic |
Cheng, Kuo-Hsing; Chen, Jian-Hung |
|
| [電機工程學系暨研究所] 會議論文 |
1997-08 |
The Charge-Transfer Feedback-Controlled Split-Path CMOS Buffer |
Cheng, Kuo-Hsing; Yang, Wei-Bin; Huang, Hong-Yi |
|
| [電機工程學系暨研究所] 會議論文 |
1997-08 |
A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process |
Cheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin |
|
| [電機工程學系暨研究所] 會議論文 |
1997-06-09 |
Design of current mode operational amplifier with differential-input and differential-output |
Cheng, Kuo-hsing; Wang, Huei-chi; 鄭國興; 王惠琪 |
|
| [電機工程學系暨研究所] 會議論文 |
1997-06-09 |
A suggestion for low-power current-sensing complementary pass-transistor logic interconnection |
鄭國興; Cheng, Kuo-hsing; Yee, Liow-yu; Chen, Jian-hung |
|
| [電機工程學系暨研究所] 會議論文 |
1996-10-13 |
A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic |
鄭國興; Cheng, Kuo-hsing; Yee, Liow yu |
|
| [電機工程學系暨研究所] 會議論文 |
1996-06-13 |
A low-power current-sensing complementary pass-transistor logic (LCSCPTL) for low-voltage high-speed applications |
鄭國興; Cheng, Kuo-hsing; Liaw, Yii-yih |
|
| [電機工程學系暨研究所] 會議論文 |
1996-05 |
True-single-phase all-N-logic differential logic (TADL) for very high-speed complex VLSI |
Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Chu, Yuan-hua; Wu, Chung-yu |
|
| [電機工程學系暨研究所] 會議論文 |
1996 |
低功率電流偵測互補式帶通電晶體邏輯設計及其在低電壓快速乘法器之使用 |
鄭國興; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 會議論文 |
1995-09 |
Rule Extraction for Isolated Speech Recognition |
Su, Mu-Chun; Cheng, Kuo-Hsing; Chin, Chieh-Ching |
|
| [電機工程學系暨研究所] 會議論文 |
1995-04-30 |
Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits |
Huang, Hong-yi; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan; Chu, Yuan-hua; Wu, Tain-shun; Wu, Chung-yu |
|
| [電機工程學系暨研究所] 會議論文 |
1995-04-30 |
A new CMOS current-sensing complementary pass-transistor logic (CSCPTL) for high-speed low-voltage applications |
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Lu, Jr-houng |
|
| [電機工程學系暨研究所] 會議論文 |
1995 |
High-speed biCHOS tristate buffer and carry lookahead adder circuit for Low-voltage operation |
鄭國興; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 會議論文 |
1995 |
High-speed BiCHOS domino logic family for low-voltage operation |
鄭國興 |
|
| [電機工程學系暨研究所] 會議論文 |
1994-05-30 |
Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit |
Tseng, Yuh-kuang; 鄭國興; Cheng, Kuo-hsing; Wu, Chung-yu |
|
| [電機工程學系暨研究所] 會議論文 |
1992-05 |
High-speed four-phase CMOS logic for complex high-speed VLSI |
Wu, Chung-yu; Cheng, Kuo-hsing; Wang, Jinn-shyan |
|
| [電機工程學系暨研究所] 會議論文 |
1989-09 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI |
Wu, Chung-yu; Cheng, Kuo-hsing; 鄭國興 |
|
| [電機工程學系暨研究所] 期刊論文 |
2009-06 |
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer |
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing; Lo, Yu-lung |
|
| [電機工程學系暨研究所] 期刊論文 |
2009-05-01 |
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique |
Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing; Lo, Yu-lung; Yang, Wei-bin; Chao, Ting-sheng; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 期刊論文 |
2003-11 |
A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop |
Cheng, Kuo-hsing; Yang, Wei-bin; Ying, Cheng-ming |
|
| [電機工程學系暨研究所] 期刊論文 |
1999-03 |
The charge-transfer feedback-controlled split-path CMOS buffer |
Cheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi |
|
| [電機工程學系暨研究所] 期刊論文 |
1998-10-01 |
Design and analysis of low-voltage current mode operational amplifier with differential-input and differential-output |
鄭國興; Cheng, Kuo-hsing; Wang, Huei-chi |
|
| [電機工程學系暨研究所] 期刊論文 |
1995-09 |
局部非同步邏輯電路的真單相位時脈架構 |
黃弘一; 鄭國興; 吳重雨 |
|
| [電機工程學系暨研究所] 期刊論文 |
1995 |
The asynchronous latched CMOS differential logic(ALCDL) and its application in dasign of high speed parallel multipliers |
Cheng, Kuo-Hsing |
|
| [電機工程學系暨研究所] 期刊論文 |
1993-04 |
無追撞四相動態邏輯CMOS的線路設計 |
鄭國興; 吳重雨; 王進賢 |
|
| [電機工程學系暨研究所] 期刊論文 |
1993-01 |
Analysis and design of a new race-free four-phase CMOS logic |
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing; Wang, Jinn-shyan |
|
| [電機工程學系暨研究所] 期刊論文 |
1991-09 |
Latched CMOS differential logic(LCDL)for complex high-speed VLSI |
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 期刊論文 |
1912-01 |
Latched CMOS differential logic(ALCDL)and its application in the design of high-speed parallel multipliers |
Wu, Chung-yu; 鄭國興; Cheng, Kuo-hsing |
|
| [電機工程學系暨研究所] 研究報告 |
2002 |
低電壓低功率之GHz鎖相迴路電路IP製作及內建測試電路設計 |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
2002 |
九十二會計年度[超大型積體電路與系統設計教育改進-聯盟發展計畫] |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
2002 |
鎖相迴路晶片之設計與相關應用之研究 |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
2001 |
低功率高輸出驅動力之GHz半數位式鎖相迴路電路之設計與實現 |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
2001 |
超大型積體電路與系統設計---IC layout&Design flow |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
2000 |
低電壓金氧半電晶體鎖相迴路晶片設計 |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
2000 |
低功率互補式金氧半呼叫器中頻鑑頻器晶片設計 |
鄭國興; 李揚漢 |
|
| [電機工程學系暨研究所] 研究報告 |
2000 |
VLSI與系統設計 |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
1999 |
高性能混合訊號積體電路與系統之設計與研究-子計畫IV：低電壓低功率數位積體電路設計合成及其應用(III) |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
1997 |
高性能混合訊號積體電路與系統之設計與研製-子計畫四：低電壓低功率數位積體電路設計合成及其於基頻數位濾波器設計應用(I) |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
1995 |
複合式專家系統及其積體電路之研究 |
鄭國興; 蘇木春 |
|
| [電機工程學系暨研究所] 研究報告 |
1995 |
類比數位混合式積體電路及系統之創新研究,晶方研製及應用研究[5/5]-類比數位混合式積體電路及系統之創新研究,晶方研製及應用研究(VI)-子計畫三-低功率高速乘法器之 |
鄭國興 |
|
| [電機工程學系暨研究所] 研究報告 |
1994 |
積體電路細胞元資料庫之開發與相關應用之研究 |
江正雄; 鄭國興; 謝景棠 |
|
