淡江大學機構典藏:作者相關文件

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"饒建奇"的相關文件

類別	日期	題名	作者
[電機工程學系暨研究所] 專利	2012	一種具有缺陷接地結構的共模濾波器	饒建奇
[電機工程學系暨研究所] 專利	2012	積體電路燒錄測試裝置	饒建奇; 錢威; 簡世超
[電機工程學系暨研究所] 專書	2016-09-09	Algorithms Opportunities and Challenges of The Big-Data Era	饒建奇
[電機工程學系暨研究所] 會議論文	2021-11-26	基於EfficientNet之導引式雙層網路應用於超解析度影像	林庭宇; 黃子盉; 閆立中; 江正雄; 饒建奇
[電機工程學系暨研究所] 會議論文	2019-11-08	測試壓縮運用單輸入通道和多個擴展比	陳冠彣; 饒建奇
[電機工程學系暨研究所] 會議論文	2015-11-28	重分佈層之避障繞線演算法	饒建奇; 王偉丞
[電機工程學系暨研究所] 會議論文	2010-08-18	An Filling Methodology for Efficient Compaction of Test Responses with Unknowns	饒建奇
[電機工程學系暨研究所] 會議論文	2010-05-30	Multi-Chains Encoding Scheme in Low-Cost ATE	饒建奇; Rau, Jiann-Chyi; Chen, Gong-Han; Wu, Po-Han
[電機工程學系暨研究所] 會議論文	2010-05-30	Multi-Cycle Compress Technique for High-Speed IP in Low-Cost Environment	饒建奇; Rau, Jiann-Chyi; Lin, Chu-Chuan; Wu, Po-Han; Chen, Gong-Han
[電機工程學系暨研究所] 會議論文	2009-12-14	A Novel Gated Scan-Cell Scheme for Low Capture Power (LCP) in At-Speed Testing	饒建奇
[電機工程學系暨研究所] 會議論文	2009-07-15	A Novel Clock Gating Scheme of Scan Chains for Capture Power Reduction	饒建奇
[電機工程學系暨研究所] 會議論文	2009-07-15	A Novel Constructive Data Compression Scheme for Shifting-in Power Reduction with Multiple Scan-chains Design	饒建奇
[電機工程學系暨研究所] 會議論文	2008-11-19	Test Slice Difference Technique for Low Power Testing	饒建奇
[電機工程學系暨研究所] 會議論文	2008-08-31	The Grid-Based Two-Layer Routing Algorithm Suitable for Cell/IP-Based Circuit Design	Liu, Chia-Jung; Lin, Yi-Chen; Rau, Jiann-Chyi
[電機工程學系暨研究所] 會議論文	2008-08-04	An Efficient Scheduling Algorithm for Testing SOC with Multi-Frequency TAM	饒建奇
[電機工程學系暨研究所] 會議論文	2008-07-22	A New Double-edge Triggered Design with Low-power consumption and High-speed	饒建奇
[電機工程學系暨研究所] 會議論文	2008-05-18	An Efficient Test-Data Compaction for Low Power VLSI Testing	饒建奇
[電機工程學系暨研究所] 會議論文	2007-08-07	A Novel High-Speed SOC Test Scheme Using Virtual TAMs	饒建奇
[電機工程學系暨研究所] 會議論文	2007-07-23	A New Algorithm for Latch-Up Check Based on Look-Up Table	饒建奇
[電機工程學系暨研究所] 會議論文	2006-05	A broadcast-based test scheme for reducing test size and application time	Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun
[電機工程學系暨研究所] 會議論文	2005-05-23	Reconfigurable multiple scan-chains for reducing test application time of SOCs	Rau, Jiann-chyi; Chien, Chih-lung; Ma, Jia-shing
[電機工程學系暨研究所] 會議論文	2005-05-23	A novel reseeding mechanism for pseudo-random testing of VLSI circuits	Rau, Jiann-chyi; Ho, Ying-fu; Wu, Po-han
[電機工程學系暨研究所] 會議論文	2004	The TAM Architecture for Optimal Testing Scheduling of SOC	Jiann-Chyi Rau; Wang-Tiao Huang; Chih-Lung Chien
[電機工程學系暨研究所] 會議論文	2004	An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains	Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi
[電機工程學系暨研究所] 會議論文	2004	The Optimal Layout-Based Multi-Scan-Chain Scheme	Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi
[電機工程學系暨研究所] 會議論文	2004	An Efficient Reseeding With Modifying Technique for Pseudo-Random-Based BIST	Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu
[電機工程學系暨研究所] 會議論文	2003-08-12	A Datapath-Based Debugging Mechanism for RTL Description	饒建奇
[電機工程學系暨研究所] 會議論文	2003	An Efficient Test Strategy for Fast Multiplier Cores	Rau, Jiann-chyi; Lin, Chia-hung; Lin, Ching-hsiu
[電機工程學系暨研究所] 會議論文	2001-08	The methods to construct imaging circuit for efficient VLSI circuit verification	饒建奇; Rau, Jiann-chyi; Chen, Y. M.; Chang, S. C.
[電機工程學系暨研究所] 期刊論文	2012-10-18	Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC	Shih, Chi-Jih; Hsu, Chih-Yao; Kuo, Chun-Yi; Li, James; Rau, Jiann-Chyi; Krishnendu Chakrabarty; Chi-Jih Shih, terrys47@hotmail.com
[電機工程學系暨研究所] 期刊論文	2011-06	Power-aware compression scheme for multiple scan-chain	Rau, Jiann-Chyi; Wu, Po-Han; Rau, Jiann-Chyi
[電機工程學系暨研究所] 期刊論文	2011-03-01	An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction	Rau, Jiann-Chyi; Wu, Chung-Lin; Wu, Po-Han; Rau, Jiann-Chyi
[電機工程學系暨研究所] 期刊論文	2011-01	Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment	Rau, Jiann-Chyi; Wu, Po-Han; Rau, Jiann-Chyi
[電機工程學系暨研究所] 期刊論文	2010-09-01	Optimal Test Access Mechanism (TAM) for Reducing Test Application Time of Core-Based SOCs	Rau, Jiann-Chyi; Wu, Po-han; Huang, Wnag-Tiao; Chien, Chih-Lung; Chen, Chien-Shiun; Rau, Jiann-Chyi
[電機工程學系暨研究所] 期刊論文	2008-11	The Efficient TAM Design for Core-Based SOCs Testing	Rau, Jiann-chyi; Wu, Po-han; Chien, Chih-lung; Wu, Chien-hsu
[電機工程學系暨研究所] 期刊論文	2008-06	A Novel Reseeding Mechanism for Improving Pseudo-Random Testing of VLSI Circuits	Rau, Jiann-chyi; Wu, Po-han; Ho, Ying-fu; Rau, Jiann-chyi
[電機工程學系暨研究所] 期刊論文	2008-06	An Efficient Scheduling Algorithm Based On Multi-frequency TAM for SOC Testing	Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing; Rau, Jiann-chyi; Wu, Po-han; Ma, Jia-shing
[電機工程學系暨研究所] 期刊論文	2004-07	以Layout為基礎的高效率多重掃描鍊最佳化	饒建奇; Rau, Jiann-chyi
[電機工程學系暨研究所] 期刊論文	2004-05	An Efficient Multi-Scan-Chain Optimization Using Physical Layout Information	Rau, Jiann-chyi; Lin, Ching-hsiu; Chang, Jun-yi
[電機工程學系暨研究所] 期刊論文	2004-05	Built-In Reseeding With Modifying Technique For Bist	Rau, Jiann-chyi; Yang, Ta-wei; Ho, Ying-fu
[電機工程學系暨研究所] 期刊論文	2004-05	The optimal testrail architecture for core-based soc testing	Rau, Jiann-chyi; Huang, Wang-tiao; Chien, Chih-lung
[電機工程學系暨研究所] 期刊論文	2001-01-01	A timing driven pseudo exhaustive testing for VLSI circuits	Chang, Shih-chieh; 饒建奇; Rau, Jiann-chyi
[電機工程學系暨研究所] 期刊論文	2000-10	Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits	Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L.
[電機工程學系暨研究所] 研究報告	2011-08	低捕捉功率快速掃描測試架構之研究	饒建奇
[電機工程學系暨研究所] 研究報告	2010	節能診斷專用晶片設計需求分析	饒建奇
[電機工程學系暨研究所] 研究報告	2009	前瞻晶片系統設計人才培育先導型計畫─教材發展：超大型積體電路測試學程　核心精進計畫	饒建奇
[電機工程學系暨研究所] 研究報告	2006	無線光通訊之智慧型盲人預警監控及導引網路系統---子計畫一：提昇私校研發能量專案計畫---無線光傳收機之研製(III)	江正雄; 郭建宏; 饒建奇
[電機工程學系暨研究所] 研究報告	2005	無線光通訊之智慧型盲人預警監控及導引網路系統-子計畫一:無線光傳收機之研製(II)	江正雄; 饒建奇; 郭建宏
[電機工程學系暨研究所] 研究報告	2001	超大型積體電路與系統設計---IP Testing	饒建奇

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