淡江大學機構典藏:Item 987654321/98020
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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/98020


    Title: Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in 90nm Process
    Authors: Yang, Wei-Bin;Lin, Yu-Yao;Lo, Yu-Lung
    Contributors: 淡江大學電機工程學系
    Keywords: 90nm CMOS process;size ratio;process-voltage-temperature (PVT);ring oscillators;threshold voltage
    Date: 2014-04-26
    Issue Date: 2014-05-20
    Abstract: In this paper, we analyze the circuit characteristic of static CMOS logics and provide the size ratio of PMOS to NMOS transistors under process, voltage and temperature (PVT) variations in 90nm CMOS process. The threshold voltage of a MOS transistor is influenced seriously under PVT variations in ultralow voltages. The performances of the static CMOS logics are unstable under those conditions. To find the best size ratio region of PMOS to NMOS transistors, NOT, NAND, NOR, and XOR gates are simulated with various PVT conditions. Four kinds of gates are designed by different ratios respectively to compose the ring oscillators. By examining operating frequency, then we analyze the change of current according to various channel length and PVT conditions. By further analyzing the simulation results, if the channel length of MOS transistors is shorter than 200nm, or the operating voltage is lower than 0.5V, then the performance of MOS transistors is unstable in 90nm CMOS process. Through the data and the simulation provided by this paper, we can design the circuits with different needs, and we can also understand how each different section of PVT variations will affect the circuit in 90nm CMOS process.
    Relation: proceedings of the 2014 International Conference on Information Science, Electronics and Electrical Engineering (ISEEE 2014), pp.1653-1656
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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