A synthesizable pseudo fractional-N clock generator with improved duty cycle output

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/96123

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Title:	A synthesizable pseudo fractional-N clock generator with improved duty cycle output
Authors:	Yang, Wei-Bin;Hsieh, Chang-Yo
Contributors:	淡江大學電機工程學系
Keywords:	Synthesizable;Clock generator;Pseudo fractional-N;Duty cycle
Date:	2011-10
Issue Date:	2014-03-03 11:24:25 (UTC+8)
Publisher:	London: Elsevier Ltd
Abstract:	A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz.
Relation:	Microelectronics Journal 42(10), pp.1099-1106
DOI:	10.1016/j.mejo.2011.07.006
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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