| 题名: | A synthesizable pseudo fractional-N clock generator with improved duty cycle output |
| 作者: | Yang, Wei-Bin;Hsieh, Chang-Yo |
| 贡献者: | 淡江大學電機工程學系 |
| 关键词: | Synthesizable;Clock generator;Pseudo fractional-N;Duty cycle |
| 日期: | 2011-10 |
| 上传时间: | 2014-03-03 11:24:25 (UTC+8) |
| 出版者: | London: Elsevier Ltd |
| 摘要: | A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz. |
| 關聯: | Microelectronics Journal 42(10), pp.1099-1106 |
| DOI: | 10.1016/j.mejo.2011.07.006 |
| 显示于类别: | [電機工程學系暨研究所] 期刊論文
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