To test core-based SoCs, an important step is to get the efficient test vectors for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test vectors at higher level than at logic level. For core vendors, they design their IP cores not only add design for testability (DFT) strategyf or its cores, but also provide the most effective test vectors for core users. Based on this issue, in this paper, we propose a method to generate pseudo-exhaustive test patterns at functional level. The proposed method can be used to generate test patterns for IP cores, especially, for soft IPs.
Relation:
第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium，頁437-440
