Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains

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Title:	Pseudo-Exhaustively Testing VLSI Circuits Using Enhanced Tree-Structured Scan Chains
Authors:	Rau, Jiann-Chyi;Kuo, Kuo-Chun;Yang, Ta-Wei
Contributors:	淡江大學電機工程學系
Keywords:	準徹底測試;超大規模積體電路;樹狀結構掃描鏈;線性回饋移位暫存器;待測電路;Pseudo-exhaustively testing;Very large scale integrated circuit(VLSI);Tree-structured scan chain;Linear feedback shift register(LFSR);Circuit under test (CUT)
Date:	2003-08
Issue Date:	2014-02-13 11:37:47 (UTC+8)
Abstract:	As the test pattern requirement of a pseudo-exhaustive testing is fewer than the traditional exhaustive testing, many approaches and architectures are proposed to implement the pseudo-exhaustive testing. Although these methods and architectures employ LFSR to generate the exhaustive pseudo random test patterns could successfully cut down the test time, the same problem of invalid test patterns should still be considered. To avoid these invalidt est patterns, it requires new strategy to solve this problem. Since different seeds of the LFSR dominate different simulation results, seed selection is not arbitrary any more. A suggestive threshold stop point for new strategy, which tries to solve "invalid test patterns" problem, is defined in this paper. Based on the concept of careful seed selection, an enhanced tree-structured scan chain is proposed to shorten total test cycle time again.
Relation:	第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium，頁305-308
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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