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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96037

    Title: A Datapath-Based Debugging Mechanism for RTL Description
    Authors: Rau, Jiann-Chyi;Chang, Yi-Yuan;Huang, Wang-Tiao
    Contributors: 淡江大學電機工程學系
    Keywords: 資料路徑;暫存器轉移層次;雜道層次;硬體描述語言;錯誤空間;Data-path;Register-transfer level (RTL);Gate level;Hardwaredescription language (HDL);Error space
    Date: 2003-08
    Issue Date: 2014-02-13 11:37:40 (UTC+8)
    Abstract: In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.
    Relation: 第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁153-156
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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