English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 52568/87720 (60%)
造訪人次 : 9373023      線上人數 : 46
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96035

    題名: Design of Low-Power Content Addressable Memory Cell
    作者: Cheng, Kuo-Hsing;Wei, Chia-Hung;Wu, Chen-Lung
    貢獻者: 淡江大學電機工程學系
    關鍵詞: 低功率;可定址記憶體記憶單元;滿足定址記憶體;隨機存取記憶體;非同步傳輸模式;Low power;Addressable memory cell;Content adddressable memory (CAM);Random-access memory (RAM);Asynchronous transfer mode (ATM)
    日期: 2003-08
    上傳時間: 2014-02-13 11:37:26 (UTC+8)
    摘要: Content Addressable Memory (CAM), a large amount of energy is generally expended charging and discharging most of the match lines on most cycles. In this paper, a new low-power CAM cell design is proposed to reduce the comparison power of CAM cell. Moreover, in the CAM word circuit design, a staticpseudo nMOS logic structure with a precomputation approach is used to effectively avoid the frequently switching in the match lines. The HSPICE simulation results are based on TSMC 0.25 m μ CMOS process with2.5 V supply voltage. The power consumption of the proposed CAM is 16.38 mW under 300 MHz operation frequency. Moreover, the power-performance metric is13.33 fJ/bit/search for random inputs.
    關聯: 第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁245-248
    顯示於類別:[電機工程學系暨研究所] 會議論文


    檔案 大小格式瀏覽次數
    Design of Low-Power Content Addressable Memory Cell_英文摘要.docx15KbMicrosoft Word122檢視/開啟



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋