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    題名: A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming
    作者: Cheng, Kuo-Hsing;Li, Po-Yu;Chen, Tsung-Shen
    貢獻者: 淡江大學電機工程學系
    關鍵詞: 數位類比轉換器;修剪;差動非線性誤差;累增非線性誤差;最小位元;Digital analog converter (DAC);Trimming;Differential non-linearity(DNL);Integral non-linearity (INL);Least significant bit (LSB)
    日期: 2003-08
    上傳時間: 2014-02-13 11:37:20 (UTC+8)
    摘要: In this paper, a 14-bit, low DNL error, 200M sample/s, current-steering digital to analog converter without trimming is proposed and analyzed. A novel feedback gain stage current mirror is proposed for improving the DAC's differential non-linearity (DNL) and integral nonlinearity(INL) characteristic. The proposed current steering DAC is designed and an experimental chip was implemented based on the TSMC 0.25um 1P5M CMOS process with a 2.5V supply voltage The post-layout simulation results show that both the DNL and INL oft his DAC are good. The DNL and INL are better than �0.06 least significant bit (LSB) and �0.06 0LSB, respectively.
    關聯: 第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium,頁205-208
    顯示於類別:[電機工程學系暨研究所] 會議論文

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