In this paper, a 14-bit, low DNL error, 200M sample/s, current-steering digital to analog converter without trimming is proposed and analyzed. A novel feedback gain stage current mirror is proposed for improving the DAC's differential non-linearity (DNL) and integral nonlinearity(INL) characteristic. The proposed current steering DAC is designed and an experimental chip was implemented based on the TSMC 0.25um 1P5M CMOS process with a 2.5V supply voltage The post-layout simulation results show that both the DNL and INL oft his DAC are good. The DNL and INL are better than �0.06 least significant bit (LSB) and �0.06 0LSB, respectively.
Relation:
第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium，頁205-208
