There exists a phase jitter problem in using the conventional direct digital frequency synthesizer (DDS)as a pulse or clock generator, and most of the existed solving methods employ the phase interpolation to generate a pulse or clock with correct time intervals. In this paper, a new phase-interpolation DDS scheme is proposed, which uses the output of the adder within the phase accumulator to provide an initial voltage on an integration capacitor in the first phase, and then performs integration operation on the integration capacitor in the second phase. Therefore, this DDS can correct the phase error at each overflow of the phase accumulator. Furthermore, no ROM tables and D/A converters are required, the proposed DDS using a two-phase integration not only provides a jitter-free clock output to reduce its spurious level, but also has a low hardware complexity.
第十四屆超大型積體電路設計暨計算機輔設計技術研討會論文摘要集=Proceedings of The 14th VLSI Design/CAD Symposium，頁565-568