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    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/96032

    題名: A High Speed Radix-4 Carry Free Division Architecture
    作者: Chiang, Jen-Shiun;Tsai, Min-Shiou;Chiu, Yi-Fang
    貢獻者: 淡江大學電機工程學系
    關鍵詞: 浮點分割;Svoboda-Tung分割;標注數位碼系統;Floating-Point Division;Svoboda-Tung Division;Signed Digit Number System
    日期: 2000-08
    上傳時間: 2014-02-13 11:37:02 (UTC+8)
    摘要: A novel floating-point division architecture with IEEE 754-1985 standard is proposed in this paper. This architecture is based on New Svoboda-Tung division algorithm and radix-4 MROR signed digit number system.The binary number to radix-4 MROR signed number conversion and prescaling of this divider are implemented together by a very simple scheme and they take very few cycle times. A new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. Based on this scheme, a 32-b/32-b divider is designed in Verilog HDL; the simulation result shows that this architecture is feasible to a real divider.
    關聯: 第十一屆超大型積體電路設計暨計算機輔助設計技術研討會技術論文集=Proceedings of the 11th VLSI Design/CAD Symposium,頁175-178
    顯示於類別:[電機工程學系暨研究所] 會議論文


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