A novel floating-point division architecture with IEEE 754-1985 standard is proposed in this paper. This architecture is based on New Svoboda-Tung division algorithm and radix-4 MROR signed digit number system.The binary number to radix-4 MROR signed number conversion and prescaling of this divider are implemented together by a very simple scheme and they take very few cycle times. A new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. Based on this scheme, a 32-b/32-b divider is designed in Verilog HDL; the simulation result shows that this architecture is feasible to a real divider.
第十一屆超大型積體電路設計暨計算機輔助設計技術研討會技術論文集=Proceedings of the 11th VLSI Design/CAD Symposium，頁175-178