A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/96026

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題名:	A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process
作者:	Cheng, Kuo-Hsing;Yee, Liow Yu;Liaw, Yii-Yih;Yang, Wei-Bin
貢獻者:	淡江大學電機工程學系
關鍵詞:	加法器;互補式金氧半導體;架構;效能比較;方塊圖;Adder;Cmos;Architecture;Performance Comparison;Block Diagram
日期:	1997-08
上傳時間:	2014-02-13 11:36:23 (UTC+8)
摘要:	This paper describes circuit techniques for fabricating a 1.2V high-speed 32-bit adder using pass-transistor logic and without changing conventional 5V CMOS process. The low- power current-sensing complementary pass-transistor logic(LCSCPTL) is used in this design for its high operating speed and low power dissipation. A carry propagation circuit technique called conditional carry selection ( CCS) is used to resolve the problem of series-connected pass transistors in the carry propagation path. Based upon the HSPICE simulation, the operation speed of the LCSCPTL is about 2.2 times higher than the CPL. The power dissipation of the LCSCPTL is lower 40% than that of the CPL.
關聯:	第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium，頁349-352
顯示於類別:	[電機工程學系暨研究所] 會議論文

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