A new low-power hihg-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer is proposed. By using the feedback-controlled split- path method, the short-circuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is saving of over 20 % in comparison to conventional CMOS tapper buffer at 100MHz operation frequency.
關聯:
第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium，頁353-356
