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    題名: A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic
    作者: Cheng, Kuo-Hsing;Chen, Jian-Hung
    貢獻者: 淡江大學電機工程學系
    關鍵詞: 互補式被動電晶體邏輯;真實單相時序;低功率;緩衝器;電路模擬;Complementary Pass-Transistor Logic;True-Single-Phase Clock;Low Power;Buffer;Circuit Simulation
    日期: 1997-08
    上傳時間: 2014-02-13 11:36:08 (UTC+8)
    摘要: This paper describes a new low-voltage low-power TSPC complementary pass-transistor logic circuit for 1.2V applications. The proposed logic circuits are implemented with only NMOS differential pass- transistor logic network and controlled by true-single-phase clock signal to form the pipelined structures. Due to the limited voltage swing and current-sensing scheme, the proposed TSPC logic circuits have certain advantages in both operation speed and power dissipation. Moreover, it can be designed and fabricated without changing the conventional 5V, 0.6μm CMOS process. Based upon the HSPICE simulation results the differential-input TSPC structure reach a 185MHz operation frequency in a adder circuit for 1.2V supply voltage.
    關聯: 第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium,頁357-360
    顯示於類別:[電機工程學系暨研究所] 會議論文

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