The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/96023

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题名:	The Design and Implementation of a 3.3V 400MHz All Digital Phase-Locked Loop
作者:	Chen, Kuang-Yuan;Chiang, Jen-Shiun
贡献者:	淡江大學電機工程學系
关键词:	全數位;鎖相迴路;電路設計;數位控制振盪器;頻率比較器;相位偵測器;All Digital;Phase Locked Loop;Circuit Design;Digital Control Oscillator;Frequency Comparator;Phase Detector
日期:	1997-08
上传时间:	2014-02-13 11:36:01 (UTC+8)
摘要:	This paper is to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6um SPDM CMOS process. The simulation shows that this chip can operate in the range between 60MHz and 400MHz, and operates at 4x the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1ns. The chip consists of 4026 MOS transistors and the core size of the VLSI layout is 923.mu.m*921.mu.m.
關聯:	第八屆超大型積體電路設計暨計算機輔助設計技術研討會論文集(VLSICAD)=Proceedings of the 8th VLSI Design/CAD Symposium，頁173-176
显示于类别:	[電機工程學系暨研究所] 會議論文

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