The tradeoff between direct-mapped caches and set-associative cachesis an important issue in the research on the performance of caches.The set-associative caches with higher associativity provide lowermiss rate, however, they suffer from longer hit access time. MRU (mostrecently used) cache is one of the set-associative caches that addressimplementation of associativity higher than two. However, the accesstime is increased because the MRU information must be fetched beforeaccessing the MRU cache. In this paper, we propose a hardware schemethat separately divides tag memory and data memory into n banksassociated with two multiplexors to reduce the sequential search time.Applying this approach to the access organization of an MRU cache canimprove the access time of the sequential MRU cache. Furthermore, thefirst hit access time of the proposed architecture is almost equal tothat of the MRU cache with parallel search, but the hardwarecomplexity is less than that of the parallel search MRU cache. Theproposed hardware scheme provides an excellent average access timewhen the associativity is 4-way, and it could be applied to parallelarchitectures, such as the multiprocessor system, to increase theoverall system performance.
Relation:
第二屆國際平行與分散式計算機應用及技術會議論文集=Proceedings,The Second International Conference on Parallel and Distributed Computing,Applications,and Technologies，頁220-227
