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    題名: A Low Power Wide Bandwidth Second-Order Continuous-Time Delta-Sigma Modulator with Single Amplifier Scheme
    作者: Jan, Yih G.;Chiang, Jen-Shiun;Tsai, Ming-Chi;Chen, Hsin-Liang;Chang, Yao-Tsung
    貢獻者: 淡江大學電機工程學系
    日期: 2006-08
    上傳時間: 2014-02-13 11:33:58 (UTC+8)
    摘要: In this paper, a low power wide bandwidth second-order continuous-time (CT) delta-sigma (.DELTA..SIGMA.) modulator with single amplifier scheme is presented. For low power consideration, we design this continuous-time modulator by the architecture of single-loop with 3-bit quantize and use only one amplifier. This continuous-time delta-sigma modulator achieves a 2 MHz signal bandwidth at 128 MHz sampling frequency operation with 68dB of dynamic range and 67.3dB of peak signal-to-noisedistortion ratio (PSNDR). The circuit is implemented by the standard 0.18-.mu.m 1P6M CMOS technology. The core area is 0.23mm/sup 2/ (0.36mm*0.64mm) and the power consumption is only 2.3-mW with 1.8-V power supply.
    關聯: 第17屆超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of the 17th VLSI Design/CAD Symposium,4頁
    顯示於類別:[電機工程學系暨研究所] 會議論文

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