The discrete cosine transform (DCT) has been widely used as the coreof digital image and video signal compression. In this paper, wepresent a high throughput 8x8 2D DCT/IDCT architecture which is wellsuited for the application in real time image or video system. Insteadof the transport RAM in traditional architecture, the overlappedrow-column operation is used that can reduce the total latency of thepipelined structure. There are several characteristics of this DCT:(1) the multiplication is accomplished by using look-up table andpartial sum adder to reduce the area and cycle time. (2) With a highthroughput rate pipelined architecture and (3) row-column overlappedtechnique is used for this DCT/IDCT. It possesses no matrixtransposition and is suitable for VLSI implementation. We havedesigned a DCT/IDCT chip using the architecture by Compass standardcell library under TSMC 0.35um 1P4M process. The chip occupies4278.4umx4278.4um and consists of 119,181 transistors. Simulationresults show the proposed architecture can work well with 100MHz thatmeets the requirement of many real-time digital video systems.
