In this paper, we present an efficient method for reducing the total length of the scan paths. The method appropriately assigns scan flip-flops into scan chains after these flip-flops being placed. We compare our proposed method with previous work based on pre-placement (PP), greedy (GR), and stable marriage (SM) assignment, and show that our method is superior to the previous approaches. We also perform our method on some of the ISCAS 89 benchmarks. The obtained results of our experiments indicate that our algorithm improves the scan chain lengths by 79%-96%and the CPU time almost increases linearly.
Proceedings of The Asian Test Symposium, 2004，頁82-87