淡江大學機構典藏:Item 987654321/95925
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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95925


    Title: An Efficient VLSI Architecture for 2-D DWT using Lifting Scheme
    Authors: Chiang, Jen-Shiun;Hsia, Chih-Hsien
    Contributors: 淡江大學電機工程學系
    Date: 2005-04
    Issue Date: 2014-02-13 11:22:03 (UTC+8)
    Abstract: In this paper, we propose a highly efficient VLSI architecture for 2-D lifting-based 5/3 filter discrete wavelet transform (DWT). The architecture is based on the pipelined and folding scheme processing to achieve near 100% hardware utilization ratio and reduce the silicon area. The advantages of the proposed DWT have the characteristics of higher hardware utilization, less memory requirement, and regular data flow. It is suitable for VLSI implementation and can be applied to real-time operating of JPEG2000 and MPEG4 applications.
    Relation: 2005年國際系統與信號研討會論文集=Proceedings of 2005 International Conference on System & Signals (ICSS2005),4頁
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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