English  |  正體中文  |  简体中文  |  Items with full text/Total items : 51931/87076 (60%)
Visitors : 8476499      Online Users : 83
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95917

    Title: 高傳輸率維特比解碼器
    Other Titles: The Design and Implementation of High Throughput Rate Viterbi Decoder
    Authors: 江正雄;李後璋
    Contributors: 淡江大學電機工程學系
    Keywords: 維特比解碼器;生還者路徑;Viterbi decoder;Trace back unit
    Date: 2005-11
    Issue Date: 2014-02-13 11:20:35 (UTC+8)
    Abstract: 此篇論文主要在陳述一種新的維特比解碼器(Viterbi decoder)的架構,目的在 提高原有IS-95, IS-2000, 8021.x的傳輸率。就原IS-95標準,其輸入頻率為10 MHz,而其傳輸率為1.22 Mbps,如果使用此架構,可將其傳輸率提升至40 Mbps,其改善倍率將近32倍。如果以IS-2000為比較(3.1 Mbps),此架構的改善 倍率,亦可達到12倍之多。而如果以現存的802.11 a/b/g,可將其原有的輸入觸 發頻率40 MHz降至10 MHz,其輸傳輸率仍可維持在27 Mbps,甚至達到40 Mbps。 並且在未來的802.11n標準下,其傳輸率必須達到100 Mbps,如輸入頻率維持在 40 MHz,此架構可提供到160 Mbps的傳輸率,仍然遠超過802.11n的標準。而且 也可大幅減少生還者路徑(Trace back unit)單元所佔積體電路的面積。
    Relation: 2005民生電子暨信號處理研討會論文集=Proceedings of Workshop on Consumer Electronics and Signal Processing,6頁
    Appears in Collections:[電機工程學系暨研究所] 會議論文

    Files in This Item:

    File SizeFormat
    高傳輸率維特比解碼器_中文摘要.docx21KbMicrosoft Word73View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback