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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95895

    Title: A Novel BIST Response Analyzer Based on TLS
    Authors: Rau, Jiann-Chyi;Jone, Wen-Ben
    Contributors: 淡江大學電機工程學系
    Keywords: 內建自測試;測試圖樣產生器;輸出響應分析;超大型積體電路;Built-In Self-Testing;Test Pattern Generator;Output Response Analysis;Vlsi
    Date: 2002-08
    Issue Date: 2014-02-13 11:17:42 (UTC+8)
    Abstract: Built-In Self-Testing (BIST) of very large scale integrated circuits(VLSI) mainly consists of two components --- test pattern generator(TPG) and output response analyze (ORA). Hence, under BIST, each of the inserted bypass storage cell (bscs) needs two flip-flops. This paper presents a novel architecture for ORA. The advantages of such architecture are that most bscs need one instead of two flip- flops, leading to the less hardware overhead shown in the experimental results.
    Relation: 2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium,頁396-399
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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