Built-In Self-Testing (BIST) of very large scale integrated circuits(VLSI) mainly consists of two components --- test pattern generator(TPG) and output response analyze (ORA). Hence, under BIST, each of the inserted bypass storage cell (bscs) needs two flip-flops. This paper presents a novel architecture for ORA. The advantages of such architecture are that most bscs need one instead of two flip- flops, leading to the less hardware overhead shown in the experimental results.
2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium，頁396-399