Low-Voltage GHz Dynamic Logic Circuit Design

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題名:	Low-Voltage GHz Dynamic Logic Circuit Design
作者:	Cheng, Kuo-Hsing;Lee, Wen-Shiuan
貢獻者:	淡江大學電機工程學系
關鍵詞:	邏輯電路設計;低電壓;功率消耗;Logic Circuit Design;Low Voltage;Power Dissipation
日期:	2002-08
上傳時間:	2014-02-13 11:17:35 (UTC+8)
摘要:	In this paper, an All-N-Block true single phase clocking logic(ANTSPC) for high operation speed and high packing density application is proposed. The ANTSPC has several advantages. Because the internal node is non-full voltage swing, it can save the dynamic power dissipation. Owing to the logic block is designed by the NMOS transistors instead of the PMOS transistors, therefore, the output loading of the Φ-Section can be reduced and the packing density of the chip is higher. Thus, the operation speed of whole pipelined system is faster than which is designed by the conventional TSPC. Finally, a 8-bit CLA adder using 0.35.mu.m 1P4M CMOS technology with 2.5V power supply could be operated on 1.25GHz clock frequency and the power/Max. frequency is 10.88 uW/MHz.
關聯:	2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium，頁113-116
顯示於類別:	[電機工程學系暨研究所] 會議論文

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