Low-Voltage GHz Dynamic Logic Circuit Design

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Proceeding > Item 987654321/95894

Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/95894

Title:	Low-Voltage GHz Dynamic Logic Circuit Design
Authors:	Cheng, Kuo-Hsing;Lee, Wen-Shiuan
Contributors:	淡江大學電機工程學系
Keywords:	邏輯電路設計;低電壓;功率消耗;Logic Circuit Design;Low Voltage;Power Dissipation
Date:	2002-08
Issue Date:	2014-02-13 11:17:35 (UTC+8)
Abstract:	In this paper, an All-N-Block true single phase clocking logic(ANTSPC) for high operation speed and high packing density application is proposed. The ANTSPC has several advantages. Because the internal node is non-full voltage swing, it can save the dynamic power dissipation. Owing to the logic block is designed by the NMOS transistors instead of the PMOS transistors, therefore, the output loading of the Φ-Section can be reduced and the packing density of the chip is higher. Thus, the operation speed of whole pipelined system is faster than which is designed by the conventional TSPC. Finally, a 8-bit CLA adder using 0.35.mu.m 1P4M CMOS technology with 2.5V power supply could be operated on 1.25GHz clock frequency and the power/Max. frequency is 10.88 uW/MHz.
Relation:	2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium，頁113-116
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

Files in This Item:

File	Size	Format
Low-Voltage GHz Dynamic Logic Circuit Design_英文摘要.docx	21Kb	Microsoft Word	131	View/Open