English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 52047/87178 (60%)
造訪人次 : 8705265      線上人數 : 174
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/95894


    題名: Low-Voltage GHz Dynamic Logic Circuit Design
    作者: Cheng, Kuo-Hsing;Lee, Wen-Shiuan
    貢獻者: 淡江大學電機工程學系
    關鍵詞: 邏輯電路設計;低電壓;功率消耗;Logic Circuit Design;Low Voltage;Power Dissipation
    日期: 2002-08
    上傳時間: 2014-02-13 11:17:35 (UTC+8)
    摘要: In this paper, an All-N-Block true single phase clocking logic(ANTSPC) for high operation speed and high packing density application is proposed. The ANTSPC has several advantages. Because the internal node is non-full voltage swing, it can save the dynamic power dissipation. Owing to the logic block is designed by the NMOS transistors instead of the PMOS transistors, therefore, the output loading of the Φ-Section can be reduced and the packing density of the chip is higher. Thus, the operation speed of whole pipelined system is faster than which is designed by the conventional TSPC. Finally, a 8-bit CLA adder using 0.35.mu.m 1P4M CMOS technology with 2.5V power supply could be operated on 1.25GHz clock frequency and the power/Max. frequency is 10.88 uW/MHz.
    關聯: 2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium,頁113-116
    顯示於類別:[電機工程學系暨研究所] 會議論文

    文件中的檔案:

    檔案 大小格式瀏覽次數
    Low-Voltage GHz Dynamic Logic Circuit Design_英文摘要.docx21KbMicrosoft Word91檢視/開啟

    在機構典藏中所有的資料項目都受到原著作權保護.

    TAIR相關文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋