To achieve a low approximation error and to simplify the circuit implementation are two important issues in the design of the direct digital frequency synthesizers (DDS) using approximation approaches . In this paper, we propose a new hardware scheme using piecewise linear approximation method to realize a sine-output DDS, which only has about a 0.005 maximum approximation error. Neither ROM lookup table existed in the conventional DDS nor small correcting data ROM used for the DDS with initial guess/correction methods is required. Furthermore, by modifying the behavior of the conventional phase accumulator, the proposed DDS also provides the flexibility for tuning frequency and a reduction of phase jitter.
2002年超大型積體電路設計暨計算機輔助設計技術研討會論文集=Proceedings of of the 2002 VLSI Design/CAD Symposium，頁496-499