實驗結果顯示，當超大型積體電路的複雜度越益成長，測試所需的輸入腳位增加幅度卻非常低。針對ISCAS’89測試電路，使用MinTest或TetraMAX產生的測試資料，本論文提出的方法，平均壓縮率為63%。比對Selective Scan Slice (SSS)方法，對於MinTest測試資料，瞬間最大轉換電能減少3倍，平均電能轉換減少6.6倍；對於TetraMAX測試資料，瞬間最大電能轉換減少2.3倍，平均電能轉換減少5.6倍。平均硬體增加幅度為MinTest的6%及TetraMAX的6.5%。 As test data volumes continue to grow, test costs also increase. To lower test costs, this paper presents a new compression method for testing large circuits, based on multiple scan-chains and an unknown structure. This method is targeted at intellectual property (IP) cores and system-on-a-chip (SoC) circuits. This study considers the shift-in power and compression ratio in low-cost ATE environments.
This study presents a new compression architecture with fixed length for testing large circuits. Because power-aware test data are not changed frequently, a selector is used to filter the unnecessary status, and buffers are used to hold the back data. A new algorithm is proposed to assign multiple scan-chains. An improved linear dependency compute method is also proposed to determine the hidden dependency between scan-chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.
The results showed that when the VLSI circuit grows in complexity, number of input pins required for testing increases slowly. The average compression ratio of the proposed method was 63% for MinTest and TetraMAX. On ISCASce for both tests, a value of 3x/6.6x was observed for MinTest and 2.3x/5.6x for TetraMAX, after comparing Selective Scan Slice (SSS) with the proposed method. The averages of hardware overhead costs were 6% for MinTest and 6.5% for TetraMAX.