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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/94523

    Title: Power-aware multi-chains encoding scheme for low-cost environment
    Other Titles: 低成本功率導向之多重鏈結串列式編碼方案
    Authors: 吳柏翰;Wu, Po-Han
    Contributors: 淡江大學電機工程學系博士班
    Keywords: 測試壓縮;低功率測試資料壓縮;單晶片系統測試;Scan based testing;Low Power Testing;Test Data Compression;System-on-Chip (SoC);Design for Testability (DfT)
    Date: 2013
    Issue Date: 2014-01-23 14:44:14 (UTC+8)
    Abstract: 隨著測試資料不斷成長,測試成本也日益增加。為了降低測試成本,針對多重鏈結串列的測試架構下,本篇論文提出一個適用於大型電路的壓縮方式。此方法對於矽智財(Intellectual Property, IP)模組,或是單晶片系(System-On-a-Chip, SoC)都非常適用。同時考量在低成本的測試設備環境中,盡可能地降低電能轉換以及增加壓縮率。


    實驗結果顯示,當超大型積體電路的複雜度越益成長,測試所需的輸入腳位增加幅度卻非常低。針對ISCAS’89測試電路,使用MinTest或TetraMAX產生的測試資料,本論文提出的方法,平均壓縮率為63%。比對Selective Scan Slice (SSS)方法,對於MinTest測試資料,瞬間最大轉換電能減少3倍,平均電能轉換減少6.6倍;對於TetraMAX測試資料,瞬間最大電能轉換減少2.3倍,平均電能轉換減少5.6倍。平均硬體增加幅度為MinTest的6%及TetraMAX的6.5%。
    As test data volumes continue to grow, test costs also increase. To lower test costs, this paper presents a new compression method for testing large circuits, based on multiple scan-chains and an unknown structure. This method is targeted at intellectual property (IP) cores and system-on-a-chip (SoC) circuits. This study considers the shift-in power and compression ratio in low-cost ATE environments.

    This study presents a new compression architecture with fixed length for testing large circuits. Because power-aware test data are not changed frequently, a selector is used to filter the unnecessary status, and buffers are used to hold the back data. A new algorithm is proposed to assign multiple scan-chains. An improved linear dependency compute method is also proposed to determine the hidden dependency between scan-chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.

    The results showed that when the VLSI circuit grows in complexity, number of input pins required for testing increases slowly. The average compression ratio of the proposed method was 63% for MinTest and TetraMAX. On ISCASce for both tests, a value of 3x/6.6x was observed for MinTest and 2.3x/5.6x for TetraMAX, after comparing Selective Scan Slice (SSS) with the proposed method. The averages of hardware overhead costs were 6% for MinTest and 6.5% for TetraMAX.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

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