English  |  正體中文  |  简体中文  |  Items with full text/Total items : 52333/87441 (60%)
Visitors : 9105723      Online Users : 271
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/94514

    Title: 應用於次臨界電壓之新型低功耗靜態隨機存取記憶體架構
    Other Titles: New ultra-low-power SRAM for sub-threshold voltage operation
    Authors: 卓易霆;Chuo, I-Ting
    Contributors: 淡江大學電機工程學系碩士班
    楊維斌;Yang, Wei-Bin
    Keywords: 次臨界;靜態隨機存取記憶體;Ultra-Low Power;SRAM;Sub-threshold
    Date: 2013
    Issue Date: 2014-01-23 14:43:47 (UTC+8)
    Abstract: 在現今的醫療或可攜式電子產品中,為了延長電池使用的時間及其使用壽命,低功率消耗的系統晶片因應而生。而在系統晶片中,記憶體通常佔有較大的面積,所以記憶體功率消耗的大小,往往影響著整個系統晶片的功率消耗。因此,本論文主要是研發能在低供應電壓下操作之新型低功耗靜態隨機存取記憶體。使用次臨界電壓作為供應電壓直接大幅降低整體操作功率。

    以整合於系統晶片之研製為考量,設計能應用於次臨界電壓之新型低功耗靜態隨機存取記憶體,完成整體SRAM的模擬與設計,再進行電路佈局與晶片製造,最後進行測試驗證。整體電路設計分為四個部份:一、記憶體單元電路架構設計,二、雙端記憶體單元寫入操作概念改變,三、新型預充電訊號產生器(Precharge Signal Generatorl:PSG)設計,四、次臨界電壓新型低功耗靜態隨機存取記憶體設計。結合以上四個步驟,目的在於設計出一個新型具可選擇性預充電機制之靜態隨機存取記憶體。

    Order to extend the battery life of today''s medical or portable electronic products, low power consumption SoC should be born. In SOC, the memory usually occupy a larger area, so the power consumption of memories, often affect the the power consumption of the entire SoC systems. Therefore, this paper is the development of low supply voltage operation of the new low-power static random access memory. Sub-threshold as the supply voltage directly significantly reduces the overall operation of power.

    To integrate the system chip development in consideration, the design can be applied in sub-threshold voltage static random access memory, after complete the simulation and design, then layout and wafer fabrication, final accomplish testing and validation. Overall circuit design is divided into four parts: first, the memory cell circuit architecture design, second, differential-ended memory cell write operation conceptual change, third, new precharge signal generator (Precharge Signal Generator: PSG) design, final, new sub-threshold voltage low-power static random access memory designs. Combining these four steps, design a new mechanism of optional pre-charging the static random access memory.

    In this paper, the SRAMs write operation concept is different from the traditional mode of operation, combined with a new precharge system to further savings in leakage power consumption so that it can be applied to advanced low-power SoC.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

    Files in This Item:

    File SizeFormat

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback