Design of a shift-and-add based hardware accelerator for color space conversion

doi:10.1007/s11554-013-0324-7

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/92247

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題名:	Design of a shift-and-add based hardware accelerator for color space conversion
作者:	Li, Shih-An;Chen, Ching-Yi;Chen, Ching-Han
貢獻者:	淡江大學電機工程學系
關鍵詞:	Hardware/software co-design;Color space converter;Hardware accelerator;SOPC
日期:	2013-02-08
上傳時間:	2013-09-18 12:20:08 (UTC+8)
出版者:	Springer
摘要:	In this paper, a Nios II processor based hardware/software co-design architecture with high expandability and development flexibility is proposed. The architecture integrates a pipelined color space converter (CSC), hardware accelerator (HA), and a LCD touch module (LTM) HA, which facilitates a high-speed implementation of RGB to YCbCr color space conversion with a real-time image display. To avoid the inefficiency of CSC circuit architecture due to massive floating-point multiplication operations in the conversion formulae, a GA-based evolutionary technique is used to realize the fast multiplierless CSC hardware architecture. Meanwhile, a pipeline design method is further applied to enhance the maximum operating frequency in circuit design. As compared to the commonly used floating-point based CSC architecture, the pipelined CSC HA in this paper has excellent advantages of low-complexity and high speed. After the mechanism is integrated into a system-on-a-programmable-chip (SOPC), the maximum operating frequency reached 168.12 MHz. That is, in every 0.11 s, the color space conversion can process a 512 × 512 image. This excellent result is practical to the fast development of different kind of image/video processing systems.
關聯:	Journal of Real-Time Image Processing 10(2), pp.193-206
DOI:	10.1007/s11554-013-0324-7
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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