A multiple frequency clock generator using wide operation frequency range phase interpolator

doi:10.1016/j.mejo.2013.04.004

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/91684

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題名:	A multiple frequency clock generator using wide operation frequency range phase interpolator
作者:	Yang, Wei-Bin;Wang, Chi-Hsiung;Yeh, Sheng-Shih;Liao, Chao-Cheng
貢獻者:	淡江大學電機工程學系
關鍵詞:	Delay-time-adjustment;Duty cycle;Multiple frequency;Phase interpolator;Voltage-controlled oscillator
日期:	2013-08-01
上傳時間:	2013-07-25 13:57:30 (UTC+8)
出版者:	London: Elsevier Ltd
摘要:	This paper presents a multiple frequency clock generator that is composed of the wide operation frequency range phase interpolator and the phase combiner. The wide operation frequency range phase interpolator is developed using a delay-time-adjustment phase interpolator (DTAPI) circuit with various oscillation frequencies for different clock domain applications. The phase combiner generates multiple clock frequencies through various phase combination inputs generated by the preceding proposed phase interpolators. The varying output transition delay time of the proposed DTAPI is the result of the various oscillation frequencies of the voltage-controlled oscillator. The test chip was fabricated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The measured phase noise and power dissipation are −87.28 dBc/Hz at 1 MHz offset frequency from 88.8 MHz and 1.32 mW, −77.47 dBc/Hz and 2.06 mW from 797.8 MHz, respectively. The duty cycle error rate of the output clock frequency is less than 1.5%.
關聯:	Microelectronics Journal 44(8), pp.688-695
DOI:	10.1016/j.mejo.2013.04.004
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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