Piscataway: Institute of Electrical and Electronics Engineers
This letter proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so that the central processing unit (CPU) time can be reduced. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results on large International Test Conference benchmark circuits show that, with very similar quality, the selected test set is 46% smaller and the CPU time is 42% faster than that of timing-aware automated test pattern generation (ATPG). With the proposed selection algorithm, small delay defect test sets are no longer very expensive to apply.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 32(6), pp.971-975