English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 58317/91854 (63%)
造訪人次 : 14018171      線上人數 : 154
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/89124

    題名: A low power sigma-delta modulator for dual-mode wide-band receiver
    作者: Chen, Hsin-Liang;Li, Yi-Tsung;Chiang, Jen-Shiun
    貢獻者: 淡江大學電機工程學系
    關鍵詞: Global system for mobile communication (GSM);Interpolative technique;Low-distortion;Sigma-delta modulator (SDM);Wideband code division multiple access (WCDMA)
    日期: 2012-05
    上傳時間: 2013-05-17 10:07:45 (UTC+8)
    出版者: New York: Springer New York LLC
    摘要: This work presents a low power cascaded sigma-delta modulator for GSM and WCDMA applications. The proposed modulator has the characteristics of wide bandwidth for WCDMA applications and low distortion in the low frequency band for GSM applications. Low-distortion and interpolative techniques are used in this modulator to enhance the performance. The low-distortion technique has not only the swing-suppressing characteristic, but it can reduce the power consumption. Moreover, the resolution can be improved even under non-linearity effects. An experimental chip is implemented in the standard 0.18-μm 1P6M CMOS technology. The measurements indicate a dynamic range of 76/68 dB and a peak signal to noise plus distortion ratio of 70/61 dB for GSM/WCDMA applications. The core area is 1 × 1.4 mm2 and the power consumption is 10.5/28 mW for GSM/WCDMA at 1.8 V.
    關聯: Analog Integrated Circuits and Signal Processing 71(2), pp.179-185
    DOI: 10.1007/s10470-011-9722-6
    顯示於類別:[電機工程學系暨研究所] 期刊論文


    檔案 描述 大小格式瀏覽次數



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋