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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/88127

    Title: 使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器
    Other Titles: Low dropout regulator with successive approximation analog to digital converter
    Authors: 高靖亞;Kao, Ching-Ya
    Contributors: 淡江大學電機工程學系碩士班
    江正雄;Chiang, Jen-Shiun
    Keywords: 低壓降線性穩壓器;LDO;連續漸近式;類比數位轉換器;SAR;ADC
    Date: 2013
    Issue Date: 2013-04-13 12:02:01 (UTC+8)
    Abstract: 論文提要內容:
    低壓降線性穩壓器有幾項主要考量的特性參數: (1) 輸出電壓差(△V)與靜態電流(Quiescent Current, Iq) (2) 線性調節率(Line Regulation, LNR) (3)負載調節率(Load Regulation, LDR);這些參數都與負載電流、精準度、穩壓時間有著密不可分的關係。整體電路可分為三大部分,第一部分為利用8位元連續漸近式類比數位轉換器架構,第二部分為功率電晶體的切換,而第三部分為比較器。
    Soc circuit will produce a non-ideal effect with process, supply voltage, and temperature, which cause the chip does not work or lead to damage to the chip in serious. And how to design a low power consumption of the circuit is an important issue.
    We will design a circuit which use of the successive approximation analog to digital converter to replace error amplifier. Therefore, this paper the target for the design of a low dropout linear regulator with successive approximation analog to digital converter architecture.
    There are several key considerations of low dropout linear regulator characteristic parameters: (1) The output voltage difference (△ V) (2) linear regulator with quiescent current (The Quiescent Current, Iq) rate (Line Regulation, LNR) (3 ) load Regulation (Load Regulation, LDR); these parameters has a close relationship with the load current, precision, settling time. The circuit can be divided into three parts, the first part of the 8-bit successive approximation analog-to-digital converter architecture, the second part is the switching of the power transistor, the last part is the comparator.
    Using the signal from SAR ADC to control the power transistor to achieve the output voltage, and reduce the quiescent current in the steady state. First, compare the input voltage and the original supply voltage to control the feedback resistor switching. Second, current changes will control turn on the power transistor or turn off the power transistor.
    The simulation results are based on 0.18μm CMOS process. The current efficiency is 99.94%. Moreover, the quiescent current of the circuit is 15.8μA in a heavy load condition.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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