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    題名: 輸入電壓低於1V之無輸出電容數位式低壓降線性穩壓器
    其他題名: A sub-1V 0.18um output-capacitor-free digitally controlled LDO
    作者: 張翔雄;Chang, Hsiang-Hsiung
    貢獻者: 淡江大學電機工程學系碩士班
    楊維斌
    關鍵詞: 低壓降線性穩壓器;輸入電壓低於1V;無輸出電容;Digita LDO;low power;Sub -1V
    日期: 2013
    上傳時間: 2013-04-13 12:01:34 (UTC+8)
    摘要: 本論文在基於低功率消耗的概念下,降低輸入電壓變為首要工作。在0.18um製程下,輸入電壓為1.8V為基本,如何降低到1V以下系統還能正常運作便是研究中的一個重要議題。低壓降線性穩壓器運用於提供穩定電壓,輸出電壓的精準度極為重要,線性調節率與負載調節率便為精準度的參考指標。
    因此,整體電路可分為三部分,第一部分為利用漸進式移位暫存控制器產生數位訊號來開啟功率電晶體以達到輸出電壓,第二部分便以移位暫存器來細微調整輸出電壓的大小,以求精準度,第三部分為比較器。在負載電流的限制下,功率電晶體的大小便為重要,在此利用8 bit的移位暫存控制器來驅使足夠大的電晶體以求達到理想的輸出電壓,由於此時輸出電壓僅為接近輸出電壓,並未達到極為準確,因此加入80級的移位暫存器來控制尺寸極小的功率電晶體,此微調範圍可包含於TT、FF、SS三種製程,使得規格都有符合預期之規格。
    透過上述的電路設計加以模擬驗證可得到一輸入電壓低於1V之無輸出電容數位式低壓降線性穩壓器,輸入電壓為0.7V,輸出電壓為0.5V。最大負載電流為20mA,與精準度有關的負載調節率可達到0.1mV/mA,而靜態電流卻僅為2.5uA。
    In this thesis, the concept based on low power consumption, and reducing the input voltage is become the top priority. In 0.18um process, the input voltage of 1.8V to basic, how to reduce to less 1V is an important topic in the study of normal operation. Low dropout regulator should be applied to provide a stable voltage, and the accuracy of output voltage is extremely important. So the line regulation and the load regulation will be the accuracy of the reference indicators.
    Therefore, the overall circuit can be divided into three parts. The first part is using SAR_Control digital signal to turn on the power transistor for achieving the output voltage. The second part is using shift register to fine tuning output voltage in order to accuracy. The third part is comparator. The size of power transistor will be important because the limit of the load current. Using 8 bit SAR_Control to drive transistor large enough for achieving the desired output voltage. The output voltage only close to the desired voltage, and it does not meet the extremely accurate. So adding 80 bit shift register to control the small size power transistor. The fine tuning range can be included in the TT,FF,SS, three kind of process, and can be meet the expected specifications.
    Though the above mentioned circuit design and simulation can be obtained a sub-1V Output-Capacitor-Free Digitally Controlled LDO. The input voltage is 0.7V, and output voltage is 0.5V. When the heavy load current is 20mA, the line regulation is 0.1mV / mA, and the quiescent is only 2.5uA.
    顯示於類別:[電機工程學系暨研究所] 學位論文

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