本論文提出一個以SOPC(System On a Programmable Chip)技術為核心之軟硬體共同設計將蟻群演算法實現於FPGA晶片上。本論文使用SOPC技術進行蟻群演算法之軟硬體電路設計，其設計方法主要分成兩個部分：(1) 選擇路徑，(2) 路徑分析。其中(1)選擇路徑屬於蟻群演算法的前置處理，需要耗費較久的運算處理時間，因此將在FPGA晶片內以設計成硬體電路，以加快處理速度。而(2)路經分析則會在NIOS II 處理器內以C語言的軟體方式實現。在本論文的實驗結果中得到可以用較少的處理時間獲得最佳的路徑資訊。 In this thesis, proposed ant colony algorithm based on a SOPC (System on a Programmable Chip) technique on the FPGA chip. In the design and implementation of ant colony algorithm based on a SOPC (System on a Programmable Chip) technique is applied to design two processing method: (1) Selecting path, (2) Path analysis. Selecting path belongs to the pre-processing of the ant colony algorithm takes a longer computing processing time, so design into a hardware circuit, in order to speed up processing. (2) path analysis will be to the C language software in the NIOS II processor. Experimental results found in this paper to the processing time can be less accurate path information.
