步進馬達控制器之FPGA設計

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 學位論文 > Item 987654321/88080

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题名:	步進馬達控制器之FPGA設計
其它题名:	FPGA-based design for stepping motor controller
作者:	陳怡君;Chen, Yi-Jiun
贡献者:	淡江大學電機工程學系碩士在職專班翁慶昌;Wong, Chang-Ching
关键词:	步進馬達;馬達控制器;Motor;Motor Controller;FPGA
日期:	2012
上传时间:	2013-04-13 11:59:51 (UTC+8)
摘要:	本論文結合AI馬達可設定速度軌跡的概念與運動控制卡的技術，以軟硬體共同設計方式將步進馬達控制器實現在FPGA晶片上。主要有三個部分：(1)RS-232通訊模組，(2)NIOS II主控制端，及(3)馬達控制器。在RS-232通訊模組上，本論文以硬體描述語言(Verilog HDL)來撰寫封包接收格式，並藉由匯流排傳輸架構(Avalon Bus)將控制命令傳送至NIOS II主控制端。在NIOS II主控制端上，本論文利用控制命令計算出加速度、定速度、減速度及這三種速度的執行時間，再透過Avalon Bus將計算結果傳送給馬達控制器。在馬達控制器設計上，本論文參考運動控制卡的功能設計各種功能模組，每個模組皆掛載至Avalon Bus上，未來可隨意新增或移除功能。由實驗結果可知，步進馬達在低中高各種速度皆可正常運作。此外，本論文所提出的架構與設計方式，讓非馬達控制專業領域的使用者可以輕鬆的操作。 In this thesis, the concepts of setting AI motor speed track and motion control card technology are combined. The hardware/software co-designed method is applied to design a stepping motor controller and implement it on the FPGA chip. There are three main parts: (1) RS-232 communication module, (2) NIOS II master, and (3) motor controller. In the RS-232 communication module, the packet receive format by Verilog Hardware Description Language (HDL) is designed. The control commands are sent to the NIOS II master through Avalon Bus. In the NIOS II master, the acceleration, maximum speed, deceleration, and three speed execution time are calculated by control commands. The calculation results are sent to the motor controller through Avalon Bus. In the motor controller, the functional design of motion control card is reference to design various functional modules. Each module is mounted to the Avalon Bus, they are free to be mounted or removed in the future. The experimental results illustrate that the motor can be normal operation in any speed. Moreover, the proposed architecture and design can let the inexperienced users operate it easily.
显示于类别:	[電機工程學系暨研究所] 學位論文

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