淡江大學機構典藏:Item 987654321/87455
English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 62830/95882 (66%)
造访人次 : 4038274      在线人数 : 564
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻


    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/87455


    题名: 加速應力允收試驗之最佳化設計
    其它题名: Optimal design for accelerated-stress acceptance test
    作者: 林琮庭;Ling, Cong-Ting
    贡献者: 淡江大學數學學系碩士班
    蔡志群;Tsai, Chih-Chun
    关键词: 最佳應力允收時間;品質特徵值;最佳試驗配置;Accelerated-stress acceptance time;quality characteristics;optimal test plan
    日期: 2013
    上传时间: 2013-04-13 11:08:29 (UTC+8)
    摘要: 隨著產品市場競爭激烈,如何縮短產品允收時間以加速出貨速
    度,即為製造商所面臨到的重要決策問題。解決此問題,可選取一
    與產品可靠度有關的品質特徵值 (quality characteristic,QC),
    且此品質特徵值隨時間逐漸衰變,再藉由提高環境應力,以加速產品的衰變,進而縮短產品的允收時間,此即所謂的加速應力允收試驗 (accelerated-stress acceptance test)。
    本文首先以一組晶片電阻器衰變資料為動機例子,建構一衰變模型。接下來,提高環境應力,探討如何執行一最佳加速應力允收試驗。換言之,在試驗總成本不超過事先給定的預算下,極小化最佳應力允收時間估計值之近似變異數,以求得最佳試驗配置 (optimal test plan)。 最後,本文以 39k ohm 晶片電阻器為例,求其最佳應力允收時間,以及在給定成本函數下的最佳試驗配置,並進行敏感度分析及模擬分析。
    Due to the intense market competition, the manufacturers face the important decision issue about how to shorten product acceptance time to speed up the shipment. In such cases, this accelerated test can be solved if there exist
    quality characteristics whose degradation over time can be related to reliability, then collecting degradation data. By elevating the environmental stress to accelerate the decay of the products, then acceptance testing time of the products can be shortened. This is called an accelerated-stress acceptance test. In this paper, motivated by a resistor data, we deal with the optimal design for a accelerated-stress acceptance test. In other words, under the constraint that the total experimental cost does not exceed a predetermined budget, the optimal decision variables are obtained by minimizing the approximate variance of the estimated optimal accelerated-stress acceptance testing time. Finally, the chip resistors on
    39k ohm is presented to illustrate the proposed method.
    显示于类别:[數學學系暨研究所] 學位論文

    文件中的档案:

    档案 大小格式浏览次数
    index.html0KbHTML141检视/开启

    在機構典藏中所有的数据项都受到原著作权保护.

    TAIR相关文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈