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顯示項目26-50 / 2102. (共85頁) << < 1 2 3 4 5 6 7 8 9 10 > >> 每頁顯示[10|25|50]項目

日期	題名	作者
2016-11-09	6-DoF Camera Motion Estimation Algorithm Using RGB-D Cameras	Tsai, Chi-Yi; Lu, Chia-Hsien; Huang, Chih-Hung
2015-11-18	6-DOF Object Posture Estimation Based on a 3D Hough Voting Algorithm	Tsai, Chi-Yi; Huang, Chih-Hung; Tsai, Shu-Hsiang
2017-06-27	6-DoF Planar Pose Estimation Based on a Real-Time Template Tracking Algorithm	Tsai, Chi-Yi; Hsu, Kuan-Jui; Liu, Ting-Yuan
2020-08-19	6-DOF Task-Oriented Grasping for Multiple Robotic Arms	Lai, Yu-Cheng; Tsai, Chi-Yi; Wong, Ching-Chang
2007-08-07	80-S/s delta sigma modulators for IR thermometer	Chiang, Jen-shiun; Chen, Hsin-liang; Chang, Yao-tsung; Ho, Meng-hsuan
2001-09	A 1.2 V 500 MHz 32-bit carry-lookahead adder	鄭國興; Cheng, Kuo-hsing; Lee, Wen-shiuan; Huang, Yung-chong
1996-10-13	A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic	鄭國興; Cheng, Kuo-hsing; Yee, Liow yu
1997-12-15	A 1.2 V low-power TSPC complementary pass transistor logic	鄭國興; Cheng, Kuo-hsing; Chen, Jian-hung
1997-08-21	A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process	鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Laiw, Yii-yih
2005-06-14	A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching	郭建宏; Kuo, Chien-hung; Tsai, Jen-chieh
2006-08	A 1V 82dB Multibit Delta-Sigma Modulator	Kuo, Chien-Hung; Chang, Kang-Shuo; Jian, Jing-Shan
2003-08	A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator	郭建宏; Kuo, Chien-hung; Kao, Tsung-kai; Liu, Shen-Iuan
1998-11-24	A 2-dimensional DCT/IDCT with overlapped row-column operation	江正雄; Chiang, Jen-shiun; Chiang, Ming-da
2005-03	A 2.5V 6.4mW 10-bit 140MS/s Digital-to-Analog Converterwith Improved Current Mirror	郭建宏; Kuo, Chien-hung; Tsai, Jen-chieh
2015-05-22	A 25MHz Crystal Less Clock Generator with Background Calibration Against Process and Temperature Variation	Yang, Wei-Bin
1998-05-31	A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock	江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan
1998-11-24	A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique	江正雄; Chiang, Jen-shiun; Chou, Pao-chu
1998	A 3.3V delta-sigma A/D converter with area-efficient and low-power digital filter for decimation on speech coding	江正雄; Chiang, Jen-shiun; Chen, Jau-liang; 賴友仁; Lai, Eugene
2006-11	A 91dB SOP-Based Low-Voltage Low-Distortion Fourth-Order 2-2 CascadedDelta-Sigma Modulator	郭建宏; Kuo, Chien-hung; Chen, Shuo-xhau; Chang, Kang-shuo
2007-01-17	A BMI Approach to Robust Controller Design for Systems with Real Parametric Uncertainties	周永山; Chou, Yung-shan
2006-05	A broadcast-based test scheme for reducing test size and application time	Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun
1986-05-24	A CAD tool in circuit analysis	余繁; Ye, Fun
1999	A carry-free radix-2 general divison algorithm and the application to the design of a 32-b/32-b divider	江正雄; Chiang, Jen-shiun; Chung, Hung-da; Tsai, Min-hsiu
1997-05-25	A cell discarding strategy to reduce cell error rate in wireless ATM networks	許獻聰; Sheu, Shiann-tsong; Wang, Chang-huang
1998-12-18	A cells splitting/merging multicast routing protocol for high-speed ATM networks	許獻聰; Sheu, Shiann-tsong; Chen, Chih-hui; Hsu, Wu-hsiao

顯示項目26-50 / 2102. (共85頁) << < 1 2 3 4 5 6 7 8 9 10 > >> 每頁顯示[10|25|50]項目