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顯示項目71-80 / 2102. (共211頁) << < 3 4 5 6 7 8 9 10 11 12 > >> 每頁顯示[10|25|50]項目

日期	題名	作者
1998-09-14	A linear current controlled delay element for low power applications	鄭國興; Cheng, Kuo-hsing; Liao, Huan-sen
1998-08	A link level sompression strategy for high-speed backbone ATM networks	許獻聰; Sheu, Shiann-tsong; Wu, Chih-chiang; Chuang, Yueh-ru
2002	A Low Power All Digital If-Discriminator Design	Cheng, K. H.; Liu, T. W.; Lin, Y. H.; Rau, J. C.
1997	A low switching voltage directional coupler with mixed type waveguide structure	Hou, Hung-ching; Hsu, Chia-lu; Sue, Chao-yung; 張文清; Chang, Wen-ching; Chang, Shih-jung
2000	A low-jitter and low-power phase-locked loop design	鄭國興; Cheng, Kuo-hsing; Liao, Huan-sen; Tzou, Lin-jiunn
1996-06-13	A low-power current-sensing complementary pass-transistor logic (LCSCPTL) for low-voltage high-speed applications	鄭國興; Cheng, Kuo-hsing; Liaw, Yii-yih
2001-05-06	A low-power high driving ability voltage control oscillator used in PLL	鄭國興; Cheng, Kuo-hsing; Yang, Wei-bin; Chung, Chun-fu
1997-12-19	A man-machine interface for the disable	蘇木春; Su, Mu-chun; Yang, M. D.; Sheu, T. F.; Hi, C. M.; Chang, Y. J.
1994-09-12	A mandarin digits recognition system based on a novel class of hyperrectangular composite neural networks	謝景棠; Hsieh, Ching-tang; 蘇木春; Su, Mu-chun; 曾慶達; Tseng, Ching-tar
1988-08-02	A maneuvering tracking method in crossing targets	Sun, Huey-min; 蔣樹民; Chiang, Shu-min

顯示項目71-80 / 2102. (共211頁) << < 3 4 5 6 7 8 9 10 11 12 > >> 每頁顯示[10|25|50]項目