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显示项目41-50 / 2102. (共211页) 1 2 3 4 5 6 7 8 9 10 > >> 每页显示[10|25|50]项目

日期	题名	作者
1998-05-31	A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock	江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan
1998-11-24	A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique	江正雄; Chiang, Jen-shiun; Chou, Pao-chu
1998	A 3.3V delta-sigma A/D converter with area-efficient and low-power digital filter for decimation on speech coding	江正雄; Chiang, Jen-shiun; Chen, Jau-liang; 賴友仁; Lai, Eugene
2006-11	A 91dB SOP-Based Low-Voltage Low-Distortion Fourth-Order 2-2 CascadedDelta-Sigma Modulator	郭建宏; Kuo, Chien-hung; Chen, Shuo-xhau; Chang, Kang-shuo
2007-01-17	A BMI Approach to Robust Controller Design for Systems with Real Parametric Uncertainties	周永山; Chou, Yung-shan
2006-05	A broadcast-based test scheme for reducing test size and application time	Rau, Jiann-chyi; Chang, Jun-yi; Chen, Chien-shiun
1986-05-24	A CAD tool in circuit analysis	余繁; Ye, Fun
1999	A carry-free radix-2 general divison algorithm and the application to the design of a 32-b/32-b divider	江正雄; Chiang, Jen-shiun; Chung, Hung-da; Tsai, Min-hsiu
1997-05-25	A cell discarding strategy to reduce cell error rate in wireless ATM networks	許獻聰; Sheu, Shiann-tsong; Wang, Chang-huang
1998-12-18	A cells splitting/merging multicast routing protocol for high-speed ATM networks	許獻聰; Sheu, Shiann-tsong; Chen, Chih-hui; Hsu, Wu-hsiao

显示项目41-50 / 2102. (共211页) 1 2 3 4 5 6 7 8 9 10 > >> 每页显示[10|25|50]项目