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    顯示項目1-50 / 2102. (共43頁)
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    日期題名作者
    2012-07-15 A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS Yang, Wei-Bin
    1997-08 A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process Cheng, Kuo-Hsing; Yee, Liow Yu;
    1997-11-29 1.2V low-power dynamic complementary-pass-transistor logic 鄭國興; Cheng, Kuo-hsing;
    1997-08 A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic Cheng, Kuo-Hsing; Chen, Jian-Hung
    2013-06 A 1.8-V 4-ppm oC Reference Current with Process and Temperature Yang, Wei-Bin; Hong, Ming-Hao;
    2013-11-05 A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration Yang, Wei-Bin
    2011 10 Gb/s 再次調變方案之設計與實現 吳帛霖; 楊淳良;
    2017-05-13 A 12-bit 600MS/s CT ΣΔ ADC for Ultrasound System Applications Yang, Wei-Bin
    2024-07-30 A 14-Bit 260-kHz BW Second-Order NS SAR ADC with Signal Charge Redistribution TechniqueA 14-Bit 260-kHz BW Second-Order NS SAR ADC with Signal Charge Redistribution Technique 3. Chuang-Hsuan Chueh, Yun-Chieh Chang, Hsin-Liang Chen, Hsiao-Hsing Chou, and Jen-Shiun Chiang
    2003-08 A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming Cheng, Kuo-Hsing; Li, Po-Yu;
    2005 2-D discrete wavelet transform with efficient parallel scheme Chiang, Jen-shiun; Hsia, Chih-hsien;
    2003-08 2.4GHz CMOS Power Amplifier with Dynamic Bias Circuits for Efficiency Improvement Chiang, Jen-Shiun; Chen, Jim-Wen
    2011-04-15 2.5-GHz hybrid oscillator with both a wide tuning range and high frequency resolution for digital PLL 施鴻源; Chiu, Huan-ke;
    2015-11-16 A 200 MHz 23 mW high-efficiency inductive link power supply circuit with differential-driven CMOS rectifier and multiple LDOs in 0.18 um CMOS process Yang, Cheng-Wei; Shih, Horng-Yuan
    2005-08-09 2005 The 16th VLSI Design/CAD Symposium Kuo, Chien-hung
    2009-06 2009，IEEE 802.11a/b/g/n多模雙頻射頻前端模組(FEM)的設計與應用 章華順; 李慶烈
    2012-11-04 A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application Yang, Wei-Bin
    2007-04 A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery Cheng, Kuo-Hsing; Chen, Chao-An;
    2008-11 A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage Liang, Yung-chih; Huang, Ching-ji;
    2012-11 3D Angle Searching System with PSO for Face Recognition Hsieh, Ching-Tang; Hu, Chia-Shing;
    2019-04-26 3D Beamforming Techniques for Indoor UWB Wireless Communications Chien, W.; Xu, J. X.;
    2015-07-18 3D FACE MODEL CONSTRUCTION BASED ON KINECT FOR FACE RECOGNITION Hsieh, Ching-Tang; Huang, Yi;
    2010-05-10 A 3D Video Rendering and Transmission Based on Clouding Computing System Wu, Tin-yu; Lee, Wei-Tsong;
    2010-12-12 A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process 施鴻源; 陳秋榜
    2024-10-25 A 5 Gb/s Receiver with Decision Feedback Equalizer and Baud-Rate Clock and Data Recovery Circuit for 8K Displays in 90 nm CMOS Process Lin, Wei-Ting; Lin, Hung-Yen;
    2016-11-09 6-DoF Camera Motion Estimation Algorithm Using RGB-D Cameras Tsai, Chi-Yi; Lu, Chia-Hsien;
    2015-11-18 6-DOF Object Posture Estimation Based on a 3D Hough Voting Algorithm Tsai, Chi-Yi; Huang, Chih-Hung;
    2017-06-27 6-DoF Planar Pose Estimation Based on a Real-Time Template Tracking Algorithm Tsai, Chi-Yi; Hsu, Kuan-Jui;
    2020-08-19 6-DOF Task-Oriented Grasping for Multiple Robotic Arms Lai, Yu-Cheng; Tsai, Chi-Yi;
    2007-08-07 80-S/s delta sigma modulators for IR thermometer Chiang, Jen-shiun; Chen, Hsin-liang;
    2001-09 A 1.2 V 500 MHz 32-bit carry-lookahead adder 鄭國興; Cheng, Kuo-hsing;
    1996-10-13 A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic 鄭國興; Cheng, Kuo-hsing;
    1997-12-15 A 1.2 V low-power TSPC complementary pass transistor logic 鄭國興; Cheng, Kuo-hsing;
    1997-08-21 A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process 鄭國興; Cheng, Kuo-hsing;
    2005-06-14 A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching 郭建宏; Kuo, Chien-hung;
    2006-08 A 1V 82dB Multibit Delta-Sigma Modulator Kuo, Chien-Hung; Chang, Kang-Shuo;
    2003-08 A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator 郭建宏; Kuo, Chien-hung;
    1998-11-24 A 2-dimensional DCT/IDCT with overlapped row-column operation 江正雄; Chiang, Jen-shiun;
    2005-03 A 2.5V 6.4mW 10-bit 140MS/s Digital-to-Analog Converterwith Improved Current Mirror 郭建宏; Kuo, Chien-hung;
    2015-05-22 A 25MHz Crystal Less Clock Generator with Background Calibration Against Process and Temperature Variation Yang, Wei-Bin
    1998-05-31 A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock 江正雄; Chiang, Jen-shiun;
    1998-11-24 A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique 江正雄; Chiang, Jen-shiun;
    1998 A 3.3V delta-sigma A/D converter with area-efficient and low-power digital filter for decimation on speech coding 江正雄; Chiang, Jen-shiun;
    2006-11 A 91dB SOP-Based Low-Voltage Low-Distortion Fourth-Order 2-2 CascadedDelta-Sigma Modulator 郭建宏; Kuo, Chien-hung;
    2007-01-17 A BMI Approach to Robust Controller Design for Systems with Real Parametric Uncertainties 周永山; Chou, Yung-shan
    2006-05 A broadcast-based test scheme for reducing test size and application time Rau, Jiann-chyi; Chang, Jun-yi;
    1986-05-24 A CAD tool in circuit analysis 余繁; Ye, Fun
    1999 A carry-free radix-2 general divison algorithm and the application to the design of a 32-b/32-b divider 江正雄; Chiang, Jen-shiun;
    1997-05-25 A cell discarding strategy to reduce cell error rate in wireless ATM networks 許獻聰; Sheu, Shiann-tsong;
    1998-12-18 A cells splitting/merging multicast routing protocol for high-speed ATM networks 許獻聰; Sheu, Shiann-tsong;

    顯示項目1-50 / 2102. (共43頁)
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