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显示项目1-25 / 2113. (共85页) 1 2 3 4 5 6 7 8 9 10 > >> 每页显示[10|25|50]项目

日期	题名	作者
2012-07-15	A 0.3V 1kb Sub-Threshold SRAM for Ultra-Low-Power Application in 90nm CMOS	Yang, Wei-Bin
1997-08	A 1.2V 32-bit CMOS Adder Design Using Conventional 5V CMOS Process	Cheng, Kuo-Hsing; Yee, Liow Yu; Liaw, Yii-Yih; Yang, Wei-Bin
1997-11-29	1.2V low-power dynamic complementary-pass-transistor logic	鄭國興; Cheng, Kuo-hsing; Chen, Jian-hung
1997-08	A 1.2V Low-Power TSPC Complementary Pass-Transistor Logic	Cheng, Kuo-Hsing; Chen, Jian-Hung
2013-06	A 1.8-V 4-ppm oC Reference Current with Process and Temperature	Yang, Wei-Bin; Hong, Ming-Hao; Yeh, Sheng-Shuh
2013-11-05	A 1.8-V Temperature Coefficient is 4.36-ppm/°C Bandgap Reference Current with Process Calibration	Yang, Wei-Bin
2011	10 Gb/s 再次調變方案之設計與實現	吳帛霖; 楊淳良; 李三良; 林淑娟
2017-05-13	A 12-bit 600MS/s CT ΣΔ ADC for Ultrasound System Applications	Yang, Wei-Bin
2024-07-30	A 14-Bit 260-kHz BW Second-Order NS SAR ADC with Signal Charge Redistribution TechniqueA 14-Bit 260-kHz BW Second-Order NS SAR ADC with Signal Charge Redistribution Technique	3. Chuang-Hsuan Chueh, Yun-Chieh Chang, Hsin-Liang Chen, Hsiao-Hsing Chou, and Jen-Shiun Chiang
2003-08	A 14-Bit, 200 MS/S Digital-To-Analog Converter Without Trimming	Cheng, Kuo-Hsing; Li, Po-Yu; Chen, Tsung-Shen
2005	2-D discrete wavelet transform with efficient parallel scheme	Chiang, Jen-shiun; Hsia, Chih-hsien; Chen, Hsin-jung
2003-08	2.4GHz CMOS Power Amplifier with Dynamic Bias Circuits for Efficiency Improvement	Chiang, Jen-Shiun; Chen, Jim-Wen
2011-04-15	2.5-GHz hybrid oscillator with both a wide tuning range and high frequency resolution for digital PLL	施鴻源; Chiu, Huan-ke; Chueh, Tzu-chan; Chen, Chiou-bang
2015-11-16	A 200 MHz 23 mW high-efficiency inductive link power supply circuit with differential-driven CMOS rectifier and multiple LDOs in 0.18 um CMOS process	Yang, Cheng-Wei; Shih, Horng-Yuan
2005-08-09	2005 The 16th VLSI Design/CAD Symposium	Kuo, Chien-hung
2009-06	2009，IEEE 802.11a/b/g/n多模雙頻射頻前端模組(FEM)的設計與應用	章華順; 李慶烈
2012-11-04	A 300mV 10MHz 4kb 10T Subthreshold SRAM for Ultralow-Power Application	Yang, Wei-Bin
2007-04	A 30Phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery	Cheng, Kuo-Hsing; Chen, Chao-An; Yang, Wei-Bin; Cho, Feng-Hsin
2008-11	A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage	Liang, Yung-chih; Huang, Ching-ji; Yang, Wei-bin
2012-11	3D Angle Searching System with PSO for Face Recognition	Hsieh, Ching-Tang; Hu, Chia-Shing; Shih, Meng-Shian; hsieh@ee.tku.edu.tw
2019-04-26	3D Beamforming Techniques for Indoor UWB Wireless Communications	Chien, W.; Xu, J. X.; Chiu, C. C.; Cheng, Y. T.; Lee, Y. L.
2015-07-18	3D FACE MODEL CONSTRUCTION BASED ON KINECT FOR FACE RECOGNITION	Hsieh, Ching-Tang; Huang, Yi; Chen, Ting-Wen; Chen, Li-Ming; Chen, Ting-Wen; Chen, Li-Ming
2010-05-10	A 3D Video Rendering and Transmission Based on Clouding Computing System	Wu, Tin-yu; Lee, Wei-Tsong; Liao, I-ju; Cheng, Hua-pu; 吳庭育; 李維聰
2010-12-12	A 400 MHz 0.934ps rms Jitter Multiplying Delay Lock Loop in 90-nm CMOS Process	施鴻源; 陳秋榜
2024-10-25	A 5 Gb/s Receiver with Decision Feedback Equalizer and Baud-Rate Clock and Data Recovery Circuit for 8K Displays in 90 nm CMOS Process	Lin, Wei-Ting; Lin, Hung-Yen; Shih, Horng-Yuan

显示项目1-25 / 2113. (共85页) 1 2 3 4 5 6 7 8 9 10 > >> 每页显示[10|25|50]项目