Siblings Proceeding [963/2104] Monograph [21/27] Chapter [11/19] Research Paper [138/460] Thesis [815/815] Patent [43/186] Audio Visual Work [0/1] Others [4/5] Collection Statistics Item counts issued in 3 years: 83(5.51%) Items With Fulltext: 1395(92.63%) Download counts of the item Download times greater than 0: 1395(100.00%) Download times greater than 10: 1395(100.00%) Total Bitstream Download Counts: 436599(35.07%) Last Update: 2025-06-03 01:28 Top Upload Loading... Top Download Loading... Recent Submissions Opamp Gain Insensitive MASH Sigma D... Inductorless CMOS Receiver Front-En... A Low-Offset Low-Noise Sigma-Delta ... Heuristic FIR Filter Design for Cas... A Low Power Sigma-Delta Modulator f... Correction to “A Low-Offset Low-Noi... A 6th Order Current- Mirror-Based G... Buck Converter Scheme with High Tra... New Phase Configuration Design Algo... Generative Adversarial Network Appl...

Jump to: [Chinese Items]   [0-9]   [ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z ] or enter the first few letters:

Showing items 1311-1320 of 1506. (151 Page(s) Totally) << < 127 128 129 130 131 132 133 134 135 136 > >> View [10|25|50] records per page

Date	Title	Authors
2000-03	The building, analyzing and simulating of a multimedia network based on CATV system	Liu, Fong-hao; Yang, C.C.; Lee, Wei-tsong
1999-03	The charge-transfer feedback-controlled split-path CMOS buffer	Cheng, Kuo-hsing; Yang, Wei-bin; Huang, Hong-yi
2018-05	The deployment of the first tidal energy capture system in Taiwan	Chen, Bang-Fuh; Chen, Lung-Chern; Huang, Chia-chen; Jiang, Z.L.; Liu, Jin-Yuan; Lu, Shian-yun; Leu, Syue-Sinn; Tien, Wen-ming; Tsai, Der-ming; Wu, Shinna
1999	The Design and Implementation of a Pipelined Multiplier Associated with a New Pass Transistor Asynchronous Control Unit	江正雄; Chiang, Jen-shiun; Liao, Jun-yao
1985	The design of a dead beat digital controller for multiple-input multiple-output system	Chang, O.; 蔣樹民; Chiang, Shu-min
2008-08	The design of a decentralized control for a class of linear time-varying interconnected dynamic delay systems using mixed H2/H-infinity optimization	黃志良
1995-02	The Design of a Fast 16-b×16-b Residue Number System Multiplier	江正雄; Chiang, Jen-Shiun; 張世昌
2010-06	The Design of a Linear Digital Pixel Sensors with Wide Dynamic Range and Logarithmic Response	Chuang, Ming-huseh; Tseng, Hsien-wei; 李揚漢; Lee, Yang-han; 詹益光; Jan, Yih-guang; Lin, Jheng-yao; Lee, Wei-chen; 余繁; Ye, Fun; Chou, Yun-hsih
1999-07	The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock	江正雄; Chiang, Jen-shiun; Chen, Kuang-yuan
2011-12	The Design of Embedded Real-time Image Processing Platform Based on SOPC Technique	Chen, Ching-yi; Li, Shin-an; Liu, Ta-kang; Chen, Kuang-yuan; Wong, Ching-chang

Showing items 1311-1320 of 1506. (151 Page(s) Totally) << < 127 128 129 130 131 132 133 134 135 136 > >> View [10|25|50] records per page