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    顯示項目51-75 / 4393. (共176頁)
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    日期題名作者
    2004-11 A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps 郭建宏; Kuo, Chien-hung;
    2001-09 A 1.2 V 500 MHz 32-bit carry-lookahead adder 鄭國興; Cheng, Kuo-hsing;
    1996-10-13 A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic 鄭國興; Cheng, Kuo-hsing;
    1997-12-15 A 1.2 V low-power TSPC complementary pass transistor logic 鄭國興; Cheng, Kuo-hsing;
    1997-08-21 A 1.2V 32-bit CMOS adder design using convertional 5V CMOS process 鄭國興; Cheng, Kuo-hsing;
    2005-06-14 A 10-bit 2.5 mW 0.27 mm2 CMOS DAC with spike-free switching 郭建宏; Kuo, Chien-hung;
    2005 A 10-bit 50Msample/s pipelined analog-to-digital converter 黃世麟; Huang, Shih-lin
    2005 A 10bits low power digital-to-analog converter 蔡仁杰; Tsai, Jen-chieh
    2006-08 A 1V 82dB Multibit Delta-Sigma Modulator Kuo, Chien-Hung; Chang, Kang-Shuo;
    2003-08 A 1V, 11-Bits Double-Sampling Delta-Sigma Modulator 郭建宏; Kuo, Chien-hung;
    1998-11-24 A 2-dimensional DCT/IDCT with overlapped row-column operation 江正雄; Chiang, Jen-shiun;
    2005-03 A 2.5V 6.4mW 10-bit 140MS/s Digital-to-Analog Converterwith Improved Current Mirror 郭建宏; Kuo, Chien-hung;
    2015-10 A 25 MHz crystal less clock generator with background calibration against process and temperature variation Yang, Wei-Bin; Hong, Ming-Hao
    2010-02 A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain with Digital-Assisted DC-Offset Calibration for Ultra-Wideband 施鴻源; Shih, Horng-yuan;
    1998-05-31 A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock 江正雄; Chiang, Jen-shiun;
    1998-11-24 A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique 江正雄; Chiang, Jen-shiun;
    1998 A 3.3V delta-sigma A/D converter with area-efficient and low-power digital filter for decimation on speech coding 江正雄; Chiang, Jen-shiun;
    A 3D Endoscopic Imaging System with Content-Adaptive Filtering and Hierarchical Similarity Analysis Chih-Hsien Hsia; Jen-Shiun Chiang;
    2006-11 A 91dB SOP-Based Low-Voltage Low-Distortion Fourth-Order 2-2 CascadedDelta-Sigma Modulator 郭建宏; Kuo, Chien-hung;
    2001-10 A bandwidth allocation/sharing/ extension protocol for multimedia over IEEE 802.11 Ad Hoc wireless LANs Sheu, Shiann-tsong; Sheu, Tzu-fang
    2009-03 A Bi-Prototype Theory of Facial Attractiveness Chang, Fu; Chou, Chien-Hsing
    2010-04 A Binarization Method with Learning-Built Rules for Document Images Produced by Cameras Chou, Chien-hsing; Lin, Wen-hsiung;
    2007-01-17 A BMI Approach to Robust Controller Design for Systems with Real Parametric Uncertainties 周永山; Chou, Yung-shan
    2005 A broadcast-based test scheme for reducing test size and application time 張俊以; Chang, Jun-yi
    2006-05 A broadcast-based test scheme for reducing test size and application time Rau, Jiann-chyi; Chang, Jun-yi;

    顯示項目51-75 / 4393. (共176頁)
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    每頁顯示[10|25|50]項目

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