A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry

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題名:	A 400 MHz 500-fs-Jitter Open-Loop DLL-Based Multi-Phase Clock Generator Utilizing an Noise-Free All-Digital Locking Detection Circuitry
作者:	Shih, Horng-Yuan;Chang, Yu-Chuan;Chen, Chun-Fan;Lin, Sheng-Kai
貢獻者:	淡江大學電機工程學系
關鍵詞:	DLL;Open-Loop;Clock Generator;Multi-Phase
日期:	2012-07-15
上傳時間:	2013-03-13 16:14:18 (UTC+8)
摘要:	An open-loop DLL-based multi-phase clock generator for low jitter applications is designed in 0.13Âµm CMOS technology. A noise-free all-digital locking detection circuitry (AD-LDC) is designed to detect whether the DLL is locked in time domain. Besides, a current-mismatch free, supplyregulated charge pump is also proposed. As the DLL operating in the open-loop mode, an rms jitter of 500 fs is achieved at the frequency of 400 MHz. The entire circuit occupies 0.01 mm2 and consumes 14 mW. The low jitter multi-phase clock generator can be applied for high-speed ADCs/DACs and wire line transceivers.
關聯:	Proceedings of the 27th International Technical Conference on Circuits/Systems, Computers and Communications
顯示於類別:	[會計學系暨研究所] 會議論文

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